전원 관리 멀티 채널 IC(PMIC)

TPS51200-EP

활성

싱크/소스 DDR 터미네이션 레귤레이터

제품 상세 정보

Vin (min) (V) 1.1 Vin (max) (V) 3.5 Vout (min) (V) -0.3 Vout (max) (V) 3.6 Features Complete Solution Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125 Iq (typ) (mA) 0.5 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3
Vin (min) (V) 1.1 Vin (max) (V) 3.5 Vout (min) (V) -0.3 Vout (max) (V) 3.6 Features Complete Solution Rating HiRel Enhanced Product Operating temperature range (°C) -55 to 125 Iq (typ) (mA) 0.5 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3
VSON (DRC) 10 9 mm² 3 x 3
  • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail
  • VLDOIN Voltage Range: 1.1 V to 3.5 V
  • Sink and Source Termination Regulator Includes
    Droop Compensation
  • Requires Minimum Output Capacitance of 20-µF
    (Typically 3 × 10-µF MLCCs) for Memory
    Termination Applications (DDR)
  • PGOOD to Monitor Output Regulation
  • EN Input
  • REFIN Input Allows for Flexible Input Tracking
    Either Directly or Through Resistor Divider
  • Remote Sensing (VOSNS)
  • ±10-mA Buffered Reference (REFOUT)
  • Built-in Soft Start, UVLO, and OCL
  • Thermal Shutdown
  • Meets DDR and DDR2 JEDEC Specifications
  • Supports DDR3, Low-Power DDR3, and DDR4
    VTT Applications
  • 10-Pin VSON Package With Thermal Pad
  • Supports Defense, Aerospace, and Medical
    Applications
    • Controlled Baseline
    • One Assembly and Test Site
    • One Fabrication Site
    • Available in Military (–55°C to 125°C)
      Temperature Range
    • Extended Product Life Cycle
    • Extended Product-Change Notification
    • Product Traceability
  • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail
  • VLDOIN Voltage Range: 1.1 V to 3.5 V
  • Sink and Source Termination Regulator Includes
    Droop Compensation
  • Requires Minimum Output Capacitance of 20-µF
    (Typically 3 × 10-µF MLCCs) for Memory
    Termination Applications (DDR)
  • PGOOD to Monitor Output Regulation
  • EN Input
  • REFIN Input Allows for Flexible Input Tracking
    Either Directly or Through Resistor Divider
  • Remote Sensing (VOSNS)
  • ±10-mA Buffered Reference (REFOUT)
  • Built-in Soft Start, UVLO, and OCL
  • Thermal Shutdown
  • Meets DDR and DDR2 JEDEC Specifications
  • Supports DDR3, Low-Power DDR3, and DDR4
    VTT Applications
  • 10-Pin VSON Package With Thermal Pad
  • Supports Defense, Aerospace, and Medical
    Applications
    • Controlled Baseline
    • One Assembly and Test Site
    • One Fabrication Site
    • Available in Military (–55°C to 125°C)
      Temperature Range
    • Extended Product Life Cycle
    • Extended Product-Change Notification
    • Product Traceability

The TPS51200-EP device is a sink and source double data rate (DDR) termination regulator specifically designed for low-input voltage, low-cost, low-noise systems where space is a key consideration.

The TPS51200-EP maintains a fast transient response and only requires a minimum output capacitance of 20 µF. The TPS51200-EP supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, Low-Power DDR3, and DDR4 VTT bus termination.

In addition, the TPS51200-EP provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications.

The TPS51200-EP is available in the thermally efficient 10-pin VSON thermal pad package, and is rated both Green and Pb-free. It is specified from –55°C to +125°C.

The TPS51200-EP device is a sink and source double data rate (DDR) termination regulator specifically designed for low-input voltage, low-cost, low-noise systems where space is a key consideration.

The TPS51200-EP maintains a fast transient response and only requires a minimum output capacitance of 20 µF. The TPS51200-EP supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, Low-Power DDR3, and DDR4 VTT bus termination.

In addition, the TPS51200-EP provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications.

The TPS51200-EP is available in the thermally efficient 10-pin VSON thermal pad package, and is rated both Green and Pb-free. It is specified from –55°C to +125°C.

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기술 자료

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3개 모두 보기
유형 직함 날짜
* Data sheet TPS51200-EP Sink and Source DDR Termination Regulator datasheet PDF | HTML 2016/06/29
* VID TPS51200-EP VID V6216610 2018/03/27
* Radiation & reliability report TPS51200MDRCTEP Reliability Report 2016/09/21

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

TPS51200EVM — TPS51200 싱크 소스 DDR 터미네이션 레귤레이터

TPS51200EVM 평가 보드인 HPA322A는 TI의 비용에 최적화된 DDR/DDR2/DDR3/LP DDR3 VTT 터미네이션 레귤레이터인 TPS51200의 성능과 특성을 평가하도록 설계되었습니다. TPS51200은 최소한의 외부 부품으로 DDR(2.5V/1.25V), DDR2(1.8V/0.9V), DDR3(1.5V/0.75V), LP DDR3(1.2V/0.6V) 사양을 지원하는 DDR 메모리에 적절한 터미네이션 전압 및 10mA 버퍼 레퍼런스 전압을 제공하도록 설계되었습니다.

사용 설명서: PDF
TI.com에서 구매 불가
시뮬레이션 모델

TPS51200 PSpice Average Model

SLVM069.ZIP (30 KB) - PSpice Model
시뮬레이션 모델

TPS51200 PSpice Transient Model (Rev. A)

SLVM068A.ZIP (38 KB) - PSpice Model
시뮬레이션 모델

TPS51200 TINA-TI Average Reference Design

SLUM150.TSC (755 KB) - TINA-TI Reference Design
시뮬레이션 모델

TPS51200 TINA-TI Average Spice Model

SLUM151.ZIP (17 KB) - TINA-TI Spice Model
시뮬레이션 모델

TPS51200 TINA-TI Start-Up Transient Reference Design

SLUM148.TSC (127 KB) - TINA-TI Reference Design
시뮬레이션 모델

TPS51200 TINA-TI Transient Spice Model

SLUM149.ZIP (18 KB) - TINA-TI Spice Model
패키지 CAD 기호, 풋프린트 및 3D 모델
VSON (DRC) 10 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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