전원 관리 멀티 채널 IC(PMIC)

TPS51200A-Q1

활성

싱크 및 소스 DDR 터미네이션 레귤레이터

제품 상세 정보

Vin (min) (V) 1.1 Vin (max) (V) 3.5 Vout (min) (V) -0.3 Vout (max) (V) 3.6 Features S3/S5 Support Rating Automotive Operating temperature range (°C) -40 to 125 Iq (typ) (mA) 0.5 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3
Vin (min) (V) 1.1 Vin (max) (V) 3.5 Vout (min) (V) -0.3 Vout (max) (V) 3.6 Features S3/S5 Support Rating Automotive Operating temperature range (°C) -40 to 125 Iq (typ) (mA) 0.5 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3
VSON (DRC) 10 9 mm² 3 x 3
  • AEC-Q100 Qualified for Automotive Applications:
    • Device Temperature Grade 1:
      –40°C ≤ TA ≤ 125°C
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C4B
  • Extended Reliability Testing
  • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail
  • VLDOIN Voltage Range: 1.1 V to 3.5 V
  • Sink and Source Termination Regulator Includes Droop Compensation
  • Requires Minimum Output Capacitance of 20-µF (typically 3 × 10-µF MLCCs) for Memory Termination Applications (DDR)
  • PGOOD to Monitor Output Regulation
  • EN Input
  • REFIN Input Allows for Flexible Input Tracking Either Directly or Through Resistor Divider
  • Remote Sensing (VOSNS)
  • ±10-mA Buffered Reference (REFOUT)
  • Built-in Soft-Start, UVLO and OCL
  • Thermal Shutdown
  • Meets DDR, DDR2 JEDEC Specifications; Supports DDR3 and Low-Power DDR3 and DDR4 VTT Applications
  • VSON-10 Package With Exposed Thermal Pad
  • AEC-Q100 Qualified for Automotive Applications:
    • Device Temperature Grade 1:
      –40°C ≤ TA ≤ 125°C
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C4B
  • Extended Reliability Testing
  • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail
  • VLDOIN Voltage Range: 1.1 V to 3.5 V
  • Sink and Source Termination Regulator Includes Droop Compensation
  • Requires Minimum Output Capacitance of 20-µF (typically 3 × 10-µF MLCCs) for Memory Termination Applications (DDR)
  • PGOOD to Monitor Output Regulation
  • EN Input
  • REFIN Input Allows for Flexible Input Tracking Either Directly or Through Resistor Divider
  • Remote Sensing (VOSNS)
  • ±10-mA Buffered Reference (REFOUT)
  • Built-in Soft-Start, UVLO and OCL
  • Thermal Shutdown
  • Meets DDR, DDR2 JEDEC Specifications; Supports DDR3 and Low-Power DDR3 and DDR4 VTT Applications
  • VSON-10 Package With Exposed Thermal Pad

The TPS51200A-Q1 device is a sink and source double-data-rate (DDR) termination regulator specifically designed for low input voltage, low-cost, low-noise systems where space is a key consideration.

The device maintains a fast transient response and only requires a minimum output capacitance of 20 µF. The device supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, and Low Power DDR3 and DDR4 VTT bus termination.

In addition, the device provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications.

The device is available in the thermally-efficient VSON-10 package, and is rated both green and Pb-free. The device is specified from –40°C to 125°C.

The TPS51200A-Q1 device is a sink and source double-data-rate (DDR) termination regulator specifically designed for low input voltage, low-cost, low-noise systems where space is a key consideration.

The device maintains a fast transient response and only requires a minimum output capacitance of 20 µF. The device supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, and Low Power DDR3 and DDR4 VTT bus termination.

In addition, the device provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications.

The device is available in the thermally-efficient VSON-10 package, and is rated both green and Pb-free. The device is specified from –40°C to 125°C.

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기술 자료

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2개 모두 보기
유형 직함 날짜
* Data sheet TPS51200A-Q1 Sink and Source DDR Termination Regulator datasheet (Rev. A) PDF | HTML 2018/12/13
Application note DDR VTT Power Solutions: A Competitive Analysis (Rev. A) 2020/07/09

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

TPS51200EVM — TPS51200 싱크 소스 DDR 터미네이션 레귤레이터

TPS51200EVM 평가 보드인 HPA322A는 TI의 비용에 최적화된 DDR/DDR2/DDR3/LP DDR3 VTT 터미네이션 레귤레이터인 TPS51200의 성능과 특성을 평가하도록 설계되었습니다. TPS51200은 최소한의 외부 부품으로 DDR(2.5V/1.25V), DDR2(1.8V/0.9V), DDR3(1.5V/0.75V), LP DDR3(1.2V/0.6V) 사양을 지원하는 DDR 메모리에 적절한 터미네이션 전압 및 10mA 버퍼 레퍼런스 전압을 제공하도록 설계되었습니다.

사용 설명서: PDF
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주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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