TPS54394
- D-CAP2 Control Mode
- Fast Transient Response
- No External Parts Required For Loop Compensation
- Compatible with Ceramic Output Capacitors
- Wide Input Voltage Range : 4.5 V to 18 V
- Output Voltage Range: 0.76 V to 7 V
- Highly Efficient Integrated FETs Optimized for
Low Duty Cycle Applications- 90 mΩ (High Side) and 60 mΩ (Low Side)
- High Initial Reference Accuracy
- Supports Constant 3 A at Both Channels
- Low-Side rDS(on) Loss-Less Current Sensing
- Fixed Soft Start : 1 ms
- Non-Sinking Pre-Biased Soft Start
- Powergood
- 700 kHz Switching Frequency
- Cycle-by-Cycle Over-Current Limit Control
- Hiccup Timer for Overload Protection
- OCL/UVLO/TSD Protections
- Adaptive Gate Drivers with Integrated Boost PMOS Switch
- OCP Constant Due To Thermally Compensated rDS(on)
with 4000ppm/°C - 16-Pin HTSSOP, 16-Pin VQFN
- Auto-Skip Eco-mode™ for High Efficiency at Light Load
The TPS54394 is a dual, adaptive on-time D-CAP2™ mode synchronous buck converter. The TPS54394 enables system designers to complete the suite of various end equipment’s power bus regulators with a cost effective, low component count, and low standby current solution. The main control loops of the TPS54394 use the D-CAP2™ mode control which provides a very fast transient response with no external compensation components. The adaptive on-time control supports seamless transition between PWM mode at higher load conditions and Eco-mode™ operation at light loads. Eco-mode™ allows the TPS54394 to maintain high efficiency during lighter load conditions. The TPS54394 is able to adapt to both low equivalent series resistance (ESR) output capacitors such as POSCAP or SP-CAP, and ultra-low ESR, ceramic capacitors. The device provides convenient and efficient operation with input voltages from 4.5V to 18V.
The TPS54394 is available in a 4.4 mm × 5 mm 16-pin TSSOP (PWP) and 4 mm × 4 mm 16-pin VQFN (RSA) package, and is specified for an ambient temperature range from –40°C to 85°C.
기술 자료
유형 | 직함 | 날짜 | ||
---|---|---|---|---|
* | Data sheet | 3A Dual Channel Synchronous Step-Down Switcher with Integrated FET datasheet (Rev. B) | 2013/08/20 | |
Application note | D-CAP2 Frequency Response Model, based on frequency domain analysis of Fixed On- | 2013/01/02 |
설계 및 개발
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TPS54394 Unencrypted PSpice Transient Model Package (Rev. B)
패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
---|---|---|
HTSSOP (PWP) | 16 | Ultra Librarian |
VQFN (RSA) | 16 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치