전원 관리 선형 및 저손실(LDO) 레귤레이터

TPS70345-EP

활성

향상된 제품, 전원 켜기 시퀀싱을 지원하는 듀얼 출력 저손실 전압 레귤레이터

이 제품의 최신 버전이 있습니다

open-in-new 대안 비교
다른 핀 출력을 지원하지만 비교 대상 장치와 동일한 기능
TPS7A88-Q1 활성 오토모티브 1A, 저잡음, 고정밀, 듀얼 채널 조정 가능한 저손실 전압 레귤레이터 Lower noise in smaller 4 x 4 VQFN
비교 대상 장치와 유사한 기능
TPS7A89 활성 2A, 저잡음, 고정밀, 듀얼 채널 조정 가능 초저손실 전압 레귤레이터 Alternative dual LDO with ultra-low-noise performance in a 4x4 WQFN package

제품 상세 정보

Output options Dual output, Fixed Output Iout (max) (A) 1 Vin (max) (V) 6 Vin (min) (V) 2.7 Vout (max) (V) 3.3 Vout (min) (V) 3.3 Fixed output options (V) 1.2, 3.3 Rating HiRel Enhanced Product Noise (µVrms) 78 PSRR at 100 KHz (dB) 22 Iq (typ) (mA) 0.18 Thermal resistance θJA (°C/W) 33 Load capacitance (min) (µF) 22 Regulated outputs (#) 2 Features Enable, Power good, Sequencing and monitoring Accuracy (%) 2 Dropout voltage (Vdo) (typ) (mV) 160 Operating temperature range (°C) -55 to 125
Output options Dual output, Fixed Output Iout (max) (A) 1 Vin (max) (V) 6 Vin (min) (V) 2.7 Vout (max) (V) 3.3 Vout (min) (V) 3.3 Fixed output options (V) 1.2, 3.3 Rating HiRel Enhanced Product Noise (µVrms) 78 PSRR at 100 KHz (dB) 22 Iq (typ) (mA) 0.18 Thermal resistance θJA (°C/W) 33 Load capacitance (min) (µF) 22 Regulated outputs (#) 2 Features Enable, Power good, Sequencing and monitoring Accuracy (%) 2 Dropout voltage (Vdo) (typ) (mV) 160 Operating temperature range (°C) -55 to 125
HTSSOP (PWP) 24 49.92 mm² 7.8 x 6.4
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of -55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • Dual Output Voltages for Split-Supply Applications
  • Selectable Power Up Sequencing for DSP Applications (See TPS704xx for Independent Enabling of Each Output)
  • Output Current Range of 1 A on Regulator 1 and 2 A on Regulator 2
  • Fast Transient Response
  • Output Voltages of 3.3-V/1.2-V
  • Open Drain Power-On Reset With 120-ms Delay
  • Open Drain Power Good for Regulator 1
  • Ultralow 185 µA (typ) Quiescent Current
  • 2 µA Input Current During Standby
  • Low Noise: 78 µVRMS Without Bypass Capacitor
  • Quick Output Capacitor Discharge Feature
  • Two Manual Reset Inputs
  • 2% Accuracy Over Load and Temperature
  • Undervoltage Lockout (UVLO) Feature
  • 24-Pin PowerPAD™ TSSOP Package
  • Thermal Shutdown Protection

PowerPAD is a trademark of Texas Instruments.

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Extended Temperature Performance of -55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • Dual Output Voltages for Split-Supply Applications
  • Selectable Power Up Sequencing for DSP Applications (See TPS704xx for Independent Enabling of Each Output)
  • Output Current Range of 1 A on Regulator 1 and 2 A on Regulator 2
  • Fast Transient Response
  • Output Voltages of 3.3-V/1.2-V
  • Open Drain Power-On Reset With 120-ms Delay
  • Open Drain Power Good for Regulator 1
  • Ultralow 185 µA (typ) Quiescent Current
  • 2 µA Input Current During Standby
  • Low Noise: 78 µVRMS Without Bypass Capacitor
  • Quick Output Capacitor Discharge Feature
  • Two Manual Reset Inputs
  • 2% Accuracy Over Load and Temperature
  • Undervoltage Lockout (UVLO) Feature
  • 24-Pin PowerPAD™ TSSOP Package
  • Thermal Shutdown Protection

PowerPAD is a trademark of Texas Instruments.

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

The TPS70345 is designed to provide a complete power management solution for Texas Instruments DSP, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of the sequencing function makes this family ideal for any Texas Instruments DSP applications with power sequencing requirement. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power on reset), manual reset inputs, and enable function, provide a complete system solution.

The TPS70345 voltage regulator offers low dropout voltage and dual outputs with power up sequence control, which is designed primarily for DSP applications. This device has a low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 47 µF low ESR capacitors.

This device has a fixed output voltage 3.3 V/1.2 V. Regulator 1 can support up to 1 A, and regulator 2 can support up to 2 A. Separate voltage inputs allow the designer to configure the source power.

Because the PMOS pass element behaves as a low-value resistor, the dropout voltage is very low (typically 160 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and independent of output loading (maximum of 250 µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal to EN\ (enable) shuts down both regulators, reducing the input current to 1 µA at TJ = 25°C.

The device is enabled when the EN\ pin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1 and VSENSE2 pins respectively.

The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2 turns on first and VOUT1 remains off until VOUT2 reaches approximately 83% of its regulated output voltage. At that time VOUT1 is turned on. If VOUT2 is pulled below 83% (i.e. overload condition) of its regulated voltage, VOUT1 will be turned off. Pulling the SEQ terminal low reverses the power-up order and VOUT1 is turned on first. The SEQ pin is connected to an internal pullup current source.

For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled).

The PG1 pin reports the voltage conditions at VOUT1. The PG1 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 1.

The TPS70345 features a RESET (SVS, POR, or power on reset). RESET\ is an active low, open drain output and requires a pullup resistor for normal operation. When pulled up, RESET\ goes to a high impedance state (i.e. logic high) after a 120 ms delay when all three of the following conditions are met. First, VIN1 must be above the undervoltage condition. Second, the manual reset (MR)\ pin must be in a high impedance state. Third, VOUT2 must be above approximately 95% of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected to MR1\ or MR2\. RESET\ can be used to drive power on reset or a low-battery indicator. If RESET\ is not used, it can be left floating.

Internal bias voltages are powered by VIN1 and require 2.7 V for full functionality. Each regulator input has an undervoltage lockout circuit that prevents each output from turning on until the respective input reaches 2.5 V.

The TPS70345 is designed to provide a complete power management solution for Texas Instruments DSP, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of the sequencing function makes this family ideal for any Texas Instruments DSP applications with power sequencing requirement. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power on reset), manual reset inputs, and enable function, provide a complete system solution.

The TPS70345 voltage regulator offers low dropout voltage and dual outputs with power up sequence control, which is designed primarily for DSP applications. This device has a low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 47 µF low ESR capacitors.

This device has a fixed output voltage 3.3 V/1.2 V. Regulator 1 can support up to 1 A, and regulator 2 can support up to 2 A. Separate voltage inputs allow the designer to configure the source power.

Because the PMOS pass element behaves as a low-value resistor, the dropout voltage is very low (typically 160 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is low and independent of output loading (maximum of 250 µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal to EN\ (enable) shuts down both regulators, reducing the input current to 1 µA at TJ = 25°C.

The device is enabled when the EN\ pin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1 and VSENSE2 pins respectively.

The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high or left open, VOUT2 turns on first and VOUT1 remains off until VOUT2 reaches approximately 83% of its regulated output voltage. At that time VOUT1 is turned on. If VOUT2 is pulled below 83% (i.e. overload condition) of its regulated voltage, VOUT1 will be turned off. Pulling the SEQ terminal low reverses the power-up order and VOUT1 is turned on first. The SEQ pin is connected to an internal pullup current source.

For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled).

The PG1 pin reports the voltage conditions at VOUT1. The PG1 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 1.

The TPS70345 features a RESET (SVS, POR, or power on reset). RESET\ is an active low, open drain output and requires a pullup resistor for normal operation. When pulled up, RESET\ goes to a high impedance state (i.e. logic high) after a 120 ms delay when all three of the following conditions are met. First, VIN1 must be above the undervoltage condition. Second, the manual reset (MR)\ pin must be in a high impedance state. Third, VOUT2 must be above approximately 95% of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected to MR1\ or MR2\. RESET\ can be used to drive power on reset or a low-battery indicator. If RESET\ is not used, it can be left floating.

Internal bias voltages are powered by VIN1 and require 2.7 V for full functionality. Each regulator input has an undervoltage lockout circuit that prevents each output from turning on until the respective input reaches 2.5 V.

다운로드 스크립트와 함께 비디오 보기 동영상

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
5개 모두 보기
유형 직함 날짜
* Data sheet Dual-Output Low-Dropout Voltage Regulators w/Power Up Sequencing datasheet (Rev. A) 2006/03/24
* VID TPS70345-EP VID V6206616 2016/06/21
* Radiation & reliability report TPS70345MPWPREP Reliability Report 2012/03/15
Application note LDO Noise Demystified (Rev. B) PDF | HTML 2020/08/18
Application note LDO PSRR Measurement Simplified (Rev. A) PDF | HTML 2017/08/09

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

패키지 CAD 기호, 풋프린트 및 3D 모델
HTSSOP (PWP) 24 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

동영상