DS15BR401
- DC to 2 Gbps Low Jitter, High Noise Immunity, Low Power Operation
- 6 dB of Pre-emphasis Drives Lossy Backplanes and Cables
- LVDS/CML/LVPECL Compatible Input, LVDS Output
- On-chip 100 Ω output termination, optional 100 Ω Input Termination
- 15 kV ESD Protection on LVDS Inputs and Outputs
- Single 3.3V Supply
- Industrial -40 to +85°C Temperature Range
- Space Saving WQFN-32 or TQFP-48 Packages
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The DS15BR400/DS15BR401 are four channel LVDS buffer/repeaters capable of data rates of up to 2 Gbps. High speed data paths and flow-through pinout minimize internal device jitter and simplify board layout, while pre-emphasis overcomes ISI jitter effects from lossy backplanes and cables. The differential inputs interface to LVDS, and Bus LVDS signals such as those on TI's 10-, 16-, and 18- bit Bus LVDS SerDes, as well as CML and LVPECL. The differential inputs and outputs of the DS15BR400 are internally terminated with 100Ω resistors to improve performance and minimize board space. The DS15BR401 does not have input termination resistors. The repeater function is especially useful for boosting signals for longer distance transmission over lossy cables and backplanes.
The DS15BR400/DS15BR401 are powered from a single 3.3V supply and consume 578 mW (typ). They operate over the full -40°C to +85°C industrial temperature range and are available in space saving WQFN-32 and TQFP-48 packages.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | DS15BR400/DS15BR401 4-Channel LVDS Buffer/Repeater with Pre-Emphasis datasheet (Rev. G) | 2013年 4月 12日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
TQFP (PFB) | 48 | Ultra Librarian |
WQFN (RTV) | 32 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。