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放大器
運算放大器 (op amps)
一般用途運算放大器

LF356

現行

單路、36-V、5-MHz、高電壓轉換率 (12-V/µs)、輸入至 V+、JFET 輸入運算放大器

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產品規格表

現在提供此產品的更新版本

open-in-new 比較替代產品
可直接投入的替代產品，相較於所比較的裝置，具備升級功能
TL071H 現行 具有操作溫度 -40°C 至 125°C 的單路、40-V、5-MHz、4-mV 偏移電壓、20-V/µs、輸入至 V+ 運算放大器 Wider temperature range (-40°C to 125°C), lower quiescent current (0.0937 mA), wider voltage range (4.5 V to 40 V), and improved offset voltage drift
TL081H 現行 具有操作溫度 -40°C 至 125°C 的單路、40-V、5.25-MHz、4-mV 偏移電壓、20-V/µs、輸入至 V+ 運算放大器 Wider supply range (4.5 V to 40 V), higher GBW (5.25 MHz), faster slew rate (20 V/us), lower offset voltage (4 mV), lower power (0.9375 mA)

LF356

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 1 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 36 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 10 Rail-to-rail In to V+ GBW (typ) (MHz) 5 Slew rate (typ) (V/µs) 12 Vos (offset voltage at 25°C) (max) (mV) 10 Iq per channel (typ) (mA) 5 Vn at 1 kHz (typ) (nV√Hz) 12 Rating Catalog Operating temperature range (°C) 0 to 70 Offset drift (typ) (µV/°C) 3 Input bias current (max) (pA) 8000 CMRR (typ) (dB) 100 Iout (typ) (A) 0.025 Architecture FET Input common mode headroom (to negative supply) (typ) (V) 3 Input common mode headroom (to positive supply) (typ) (V) 0.1 Output swing headroom (to negative supply) (typ) (V) 2 Output swing headroom (to positive supply) (typ) (V) -2
Number of channels 1 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 36 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 10 Rail-to-rail In to V+ GBW (typ) (MHz) 5 Slew rate (typ) (V/µs) 12 Vos (offset voltage at 25°C) (max) (mV) 10 Iq per channel (typ) (mA) 5 Vn at 1 kHz (typ) (nV√Hz) 12 Rating Catalog Operating temperature range (°C) 0 to 70 Offset drift (typ) (µV/°C) 3 Input bias current (max) (pA) 8000 CMRR (typ) (dB) 100 Iout (typ) (A) 0.025 Architecture FET Input common mode headroom (to negative supply) (typ) (V) 3 Input common mode headroom (to positive supply) (typ) (V) 0.1 Output swing headroom (to negative supply) (typ) (V) 2 Output swing headroom (to positive supply) (typ) (V) -2
PDIP (P) 8 92.5083 mm² 9.81 x 9.43 SOIC (D) 8 29.4 mm² 4.9 x 6
  • Advantages
    • Replace Expensive Hybrid and Module FET
      Op Amps
    • Rugged JFETs Allow Blow-Out Free Handling
      Compared With MOSFET Input Devices
    • Excellent for Low Noise Applications Using
      Either High or Low Source Impedance–Very
      Low 1/f Corner
    • Offset Adjust Does Not Degrade Drift or
      Common-Mode Rejection as in Most
      Monolithic Amplifiers
    • New Output Stage Allows Use of Large
      Capacitive Loads (5,000 pF) Without Stability
      Problems
    • Internal Compensation and Large Differential
      Input Voltage Capability
  • Common Features
    • Low Input Bias Current: 30 pA
    • Low Input Offset Current: 3 pA
    • High Input Impedance: 1012 Ω
    • Low Input Noise Current: 0.01 pA/√Hz
    • High Common-Mode Rejection Ratio: 100 dB
    • Large DC Voltage Gain: 106 dB
  • Uncommon Features
    • Extremely Fast Settling Time to 0.01%:
      • 4 µs for the LFx55 devices
      • 1.5 µs for the LFx56
      • 1.5 µs for the LFx57 (AV = 5)
    • Fast Slew Rate:
      • 5 V/µs for the LFx55
      • 12 V/µs for the LFx56
      • 50 V/µs for the LFx57 (AV = 5)
    • Wide Gain Bandwidth:
      • 2.5 MHz for the LFx55 devices
      • 5 MHz for the LFx56
      • 20 MHz for the LFx57 (AV = 5)
    • Low Input Noise Voltage:
      • 20 nV/√Hz for the LFx55
      • 12 nV/√Hz for the LFx56
      • 12 nV/√Hz for the LFx57 (AV = 5)
  • Advantages
    • Replace Expensive Hybrid and Module FET
      Op Amps
    • Rugged JFETs Allow Blow-Out Free Handling
      Compared With MOSFET Input Devices
    • Excellent for Low Noise Applications Using
      Either High or Low Source Impedance–Very
      Low 1/f Corner
    • Offset Adjust Does Not Degrade Drift or
      Common-Mode Rejection as in Most
      Monolithic Amplifiers
    • New Output Stage Allows Use of Large
      Capacitive Loads (5,000 pF) Without Stability
      Problems
    • Internal Compensation and Large Differential
      Input Voltage Capability
  • Common Features
    • Low Input Bias Current: 30 pA
    • Low Input Offset Current: 3 pA
    • High Input Impedance: 1012 Ω
    • Low Input Noise Current: 0.01 pA/√Hz
    • High Common-Mode Rejection Ratio: 100 dB
    • Large DC Voltage Gain: 106 dB
  • Uncommon Features
    • Extremely Fast Settling Time to 0.01%:
      • 4 µs for the LFx55 devices
      • 1.5 µs for the LFx56
      • 1.5 µs for the LFx57 (AV = 5)
    • Fast Slew Rate:
      • 5 V/µs for the LFx55
      • 12 V/µs for the LFx56
      • 50 V/µs for the LFx57 (AV = 5)
    • Wide Gain Bandwidth:
      • 2.5 MHz for the LFx55 devices
      • 5 MHz for the LFx56
      • 20 MHz for the LFx57 (AV = 5)
    • Low Input Noise Voltage:
      • 20 nV/√Hz for the LFx55
      • 12 nV/√Hz for the LFx56
      • 12 nV/√Hz for the LFx57 (AV = 5)

The LFx5x devices are the first monolithic JFET input operational amplifiers to incorporate well-matched, high-voltage JFETs on the same chip with standard bipolar transistors (BI-FET™ Technology). These amplifiers feature low input bias and offset currents/low offset voltage and offset voltage drift, coupled with offset adjust, which does not degrade drift or common-mode rejection. The devices are also designed for high slew rate, wide bandwidth, extremely fast settling time, low voltage and current noise and a low 1/f noise corner.

The LFx5x devices are the first monolithic JFET input operational amplifiers to incorporate well-matched, high-voltage JFETs on the same chip with standard bipolar transistors (BI-FET™ Technology). These amplifiers feature low input bias and offset currents/low offset voltage and offset voltage drift, coupled with offset adjust, which does not degrade drift or common-mode rejection. The devices are also designed for high slew rate, wide bandwidth, extremely fast settling time, low voltage and current noise and a low 1/f noise corner.
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技術文件

star =TI 所選的此產品重要文件
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檢視所有 11
類型 標題 日期
* Data sheet LFx5x JFET Input Operational Amplifiers datasheet (Rev. D) PDF | HTML 2015年 11月 30日
E-book The Signal e-book: A compendium of blog posts on op amp design topics 2017年 3月 28日
Application note AN-272 Op Amp Booster Designs (Rev. B) 2013年 4月 23日
Application note AN-263 Sine Wave Generation Techniques (Rev. C) 2013年 4月 22日
Application note Effect of Heavy Loads on Accuracy and Linearity of Op Amp Circuits (Rev. B) 2013年 4月 22日
Application note Data Acq Using ADC0816 & ADC0817 8-Bit ADC w/On-Chip 16 Chan Multiplexr 2004年 5月 10日
Application note AN-293 Control Applications of CMOS DACs 2004年 5月 10日
Application note AN-253 LH0024 and LH0032 High Speed Op Amp Applications 2004年 5月 2日
Application note AN-275 CMOS D/A Converters Match Most Microprocessors 2004年 5月 2日
Application note AN-447 Protection Schemes for BI-FET Amplifiers and Switches 2004年 5月 2日
Application note Get Fast Stable Response From Improved Unity-Gain Followers 2002年 10月 2日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

AMP-PDK-EVM — 放大器性能開發套件評估模組

放大器性能開發套件 (PDK) 是一款評估模組 (EVM) 套件，可測試通用運算放大器 (op amp) 參數，並與大多數運算放大器和比較器相容。EVM 套件提供主板和多個插槽式子卡選項，可滿足封裝需求，使工程師能夠快速評估和驗證裝置性能。

AMP-PDK-EVM 套件支援五種最熱門的業界標準封裝，包括：

  • D (SOIC-8 和 SOIC-14)
  • PW (TSSOP-14)
  • DGK (VSSOP-8)
  • DBV (SOT23-5 和 SOT23-6)
  • DCK (SC70-5 和 SC70-6)
使用指南: PDF | HTML
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開發板

DIP-ADAPTER-EVM — DIP 轉接器評估模組

Speed up your op amp prototyping and testing with the DIP-Adapter-EVM, which provides a fast, easy and inexpensive way to interface with small, surface-mount ICs. You can connect any supported op amp using the included Samtec terminal strips or wire them directly to existing circuits.

The (...)

使用指南: PDF
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模擬型號

LF356 PSPICE Model

SNOM255.ZIP (1 KB) - PSpice Model
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計算工具

ANALOG-ENGINEER-CALC — 類比工程師計算機

The Analog Engineer’s Calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting op-amp gain with feedback (...)
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設計工具

CIRCUIT060013 — 具有 T 網路回饋電路的反相放大器

此設計可反轉輸入訊號 VIN，並使用 1000 V/V 或 60 dB 訊號增益。具有 T 回饋網路的反相放大器可在沒有較小 R4 值或超大回饋電阻器值的情況下獲得高增益。
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設計工具

CIRCUIT060015 — 可調式參考電壓電路

此電路結合反相及非反相放大器，讓參考電壓可從負輸入電壓向上調整至輸入電壓。可加入增益以提高最大負參考位準。
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設計工具

CIRCUIT060074 — 具有比較器電路的高壓側電流感測

此高壓側電流感測解決方案使用一個具有軌對軌輸入共模範圍的比較器，若負載電流上升到 1 A 以上，便在比較器輸出 (COMP OUT) 建立過電流警示 (OC 警示) 訊號。此實作中的 OC 訊號為低電位作動。因此當超過 1-A 閾值時，比較器輸出會變低。實作磁滯後會在負載電流降低至 0.5 A (減少 50%) 時，讓 OC-Alert 返回邏輯高狀態。此電路利用開漏輸出比較器，為控制數位邏輯輸入針腳而進行電平轉換輸出高邏輯電平。對於需要驅動 MOSFET 開關閘極的應用，建議使用具推挽輸出的比較器。
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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
要求
模擬工具

TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
PDIP (P) 8 Ultra Librarian
SOIC (D) 8 Ultra Librarian
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