SN75DP129
- DisplayPort Physical Layer Input Port to TMDS Physical Layer Output Port
- Integrated TMDS Level Translator With Receiver Equalization
- Supports Data Rates up to 2.5 Gbps
- Integrated I2C Logic Block for DVI / HDMI Connector Recognition
- Integrated Active I2C Buffer
- Enhanced ESD: 12 kV on all Pins
- Enhanced Commercial Temperature Range: 0°C to 85°C
- 36 Pin 6 × 6 QFN Package
- APPLICATIONS
- Personal Computer Market
- DP/TMDS Hardware Key (Dongle)
- Desktop PC
- Notebook PC
- Docking Station
- Standalone Video Card
- Personal Computer Market
The SN75DP129 is a Dual-Mode DisplayPort input to Transition-Minimized Differential Signaling (TMDS) output. The TMDS output has a built-in level translator, compliant with Digital Visual Interface 1.0 (DVI) and High Definition Multimedia Interface 1.3 (HDMI) standards. The SN75DP129 is specified up to a maximum data rate of 2.5 Gbps, supporting resolutions greater then 1920 x 1200 or HDTV 12-bit color depth at 1080p (progressive scan).
An integrated Active I2C buffer isolates the capacitive loading of the source system from that of the sink and interconnecting cable. This isolation improves overall signal integrity of the system and provides greater design margin within the source system for DVI / HDMI compliance testing.
A logic block was designed into the SN75DP129 to assist with TMDS connector identification. Through the use of the I2C_EN pin, this logic block can be enabled to indicate the translated port is an HDMI port; therefore legally supporting HDMI content.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | DisplayPort to TMDS Translator datasheet (Rev. A) | 2008年 3月 4日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
VQFN (RHH) | 36 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點