封裝資訊
| 封裝 | 針腳 WSON (DSQ) | 10 |
| 操作溫度範圍 (°C) -40 to 105 |
| 包裝數量 | 運送業者 3,000 | LARGE T&R |
TPS51206 的特色
- Supply Input Voltage: Supports 3.3-V Rail and 5-V Rail
- VLDOIN Input Voltage Range: VTT+0.4 V to 3.5 V
- VTT Termination Regulator
- Output Voltage Range: 0.5 V to 0.9 V
- 2-A Peak Sink and Source Current
- Requires Only 10-µF MLCC Output Capacitor
- ±20 mV Accuracy
- VTTREF Buffered
Reference
- VDDQ/2 ± 1% Accuracy
- 10-mA Sink and Source Current
- Supports High-Z in S3 and Soft-Stop in S4 and S5 with S3 and S5 Inputs
- Overtemperature Protection
- 10-Pin, 2 mm × 2 mm SON (DSQ) Package
TPS51206 的說明
The TPS51206 device is a sink and source double date rate (DDR) termination regulator with VTTREF buffered reference output. It is specifically designed for low-input voltage, low-cost, low-external component count systems where space is a key consideration. The device maintains fast transient response and only requires 1 × 10-µF of ceramic output capacitance. The device supports a remote sensing function and all power requirements for DDR2, DDR3 and Low-Power DDR3 (DDR3L), and DDR4 VTT bus. The VTT current capability is ±2-A peak. The device supports all of the DDR power states, putting VTT to High-Z in S3 state (suspend to RAM) and discharging VTT and VTTREF in S4 or S5 state (suspend to disk).
The TPS51206 device is available in 10-Pin, 2 mm × 2 mm SON (DSQ) PowerPAD™ package and specified from –40°C to 105°C.