封裝資訊
| 封裝 | 針腳 SOIC (DW) | 16 |
| 操作溫度範圍 (°C) -55 to 125 |
| 包裝數量 | 運送業者 2,000 | LARGE T&R |
UC2825A-EP 的特色
- Improved Version of the UC2825 PWM
- Compatible With Voltage-Mode or Current-Mode Control Methods
- Practical Operation at Switching Frequencies to 1 MHz
- 50-ns Propagation Delay to Output
- High-Current Dual Totem-Pole Outputs
(2-A Peak) - Trimmed Oscillator Discharge Current
- Low 100-µA Startup Current
- Pulse-by-Pulse Current-Limiting Comparator
- Latched Overcurrent Comparator With Full Cycle Restart
- APPLICATIONS
- Controlled Baseline
- One Assembly/Test Site
- One Fabrication Site
- Available in Military (–55°C/125°C) Temperature Range(1)
- Extended Product Life Cycle
- Extended Product-Change Notification
- Product Traceability
(1) Additional temperature ranges are available - contact factory
UC2825A-EP 的說明
The UC2825A-EP pulse width modulation (PWM) controller is an improved version of the standard UC2825. Performance enhancements have been made to several of the circuit blocks. Error amplifier gain bandwidth product is 12 MHz, while input offset voltage is 2 mV. Current-limit threshold is specified to a tolerance of 5%. Oscillator discharge current is specified at 10 mA for accurate dead-time control. Frequency accuracy is improved to 6%. Startup supply current, typically 100 µA, is ideal for off-line applications. The output drivers are redesigned to actively sink current during undervoltage lockout (UVLO) at no expense to the startup current specification. In addition, each output is capable of 2-A peak currents during transitions.
Functional improvements also have been implemented in this family. The UC2825A-EP shutdown comparator is now a high-speed overcurrent comparator with a threshold of 1.2 V. The overcurrent comparator sets a latch that ensures full discharge of the soft-start capacitor before allowing a restart. While the fault latch is set, the outputs are in the low state. In the event of continuous faults, the soft-start capacitor is fully charged before discharge to ensure that the fault frequency does not exceed the designed soft-start period. The UC2825 CLOCK pin is CLK/LEB in the UC2825A-EP. This pin combines the functions of clock output and leading-edge blanking adjustment and has been buffered for easier interfacing.
The UC2825A-EP has dual alternating outputs and the same pin configuration as UC2825. UVLO thresholds are identical to the original UC2825.
Consult the application report, The UC3823A,B and UC2825A,B Enhanced Generation of PWM Controllers, literature number SLUA125, for detailed technical and applications information.