Let us analyze why high duty cycle can cause high current stress in bootstrap diode and assume power supply V₂ do not involve in first. Taking optimizer as the example, at the end of transition process from buck mode to pass through mode, high side FET duty cycle can nearly approach 100% and duty cycle of low side FET can nearly approach 0%, Figure 3-1 shows the time diagram of PWM signal. There are four operation modes during the transition period. Figure 3-2 shows the equivalent circuits of system.

• Blue Line: low side MOSFET gate to source PWM signal
• Green Line: high side gate to source PWM signal

In practical applications, a common way to create these power supplies is to use fly-buck or fly-back topology with multiple windings. Assume two power supplies is produced by different windings, and connected to the VDD, GND, HB, HS separately. for better understanding, analysis for different modes are accomplished as follows.