Startseite Schnittstelle Andere Schnittstellen

DS90CF388

AKTIV

+3,3 V-Dual-Pixel-LVDS-Display-Schnittstelle (LDI)-SVGA/QXGA-Empfänger

Produktdetails

Protocols Catalog Rating Catalog Operating temperature range (°C) -10 to 70
Protocols Catalog Rating Catalog Operating temperature range (°C) -10 to 70
QFP (NEZ) 100 256 mm² 16 x 16
  • Complies with OpenLDI Specification for Digital Display Interfaces
  • 32.5 to 112/170MHz Clock Support for DS90C387, 40 to 112MHz Clock Support for DS90CF388
  • Supports SVGA through QXGA Panel Resolutions
  • Drives Long, Low Cost Cables
  • Up to 5.38Gbps Bandwidth
  • Pre-Emphasis Reduces Cable Loading Effects
  • DC Balance Data Transmission Provided by Transmitter Reduces ISI Distortion
  • Cable Deskew of +/−1 LVDS Data Bit Time (up to 80 MHz Clock Rate) of Pair-to-Pair Skew at Receiver Inputs; Intra-Pair Skew Tolerance of 300ps
  • Dual Pixel Architecture Supports Interface to GUI and Timing Controller; Optional Single Pixel Transmitter Inputs Support Single Pixel GUI Interface
  • Transmitter Rejects Cycle-to-Cycle Jitter
  • 5V Tolerant on Data and Control Input Pins
  • Programmable Transmitter Data and Control Strobe Select (Rising or Falling Edge Strobe)
  • Backward Compatible Configuration Select with FPD-Link
  • Optional Second LVDS Clock for Backward Compatibility w/ FPD-Link
  • Support for Two Additional User-Defined Control Signals in DC Balanced Mode
  • Compatible with ANSI/TIA/EIA-644-1995 LVDS Standard

All trademarks are the property of their respective owners.

  • Complies with OpenLDI Specification for Digital Display Interfaces
  • 32.5 to 112/170MHz Clock Support for DS90C387, 40 to 112MHz Clock Support for DS90CF388
  • Supports SVGA through QXGA Panel Resolutions
  • Drives Long, Low Cost Cables
  • Up to 5.38Gbps Bandwidth
  • Pre-Emphasis Reduces Cable Loading Effects
  • DC Balance Data Transmission Provided by Transmitter Reduces ISI Distortion
  • Cable Deskew of +/−1 LVDS Data Bit Time (up to 80 MHz Clock Rate) of Pair-to-Pair Skew at Receiver Inputs; Intra-Pair Skew Tolerance of 300ps
  • Dual Pixel Architecture Supports Interface to GUI and Timing Controller; Optional Single Pixel Transmitter Inputs Support Single Pixel GUI Interface
  • Transmitter Rejects Cycle-to-Cycle Jitter
  • 5V Tolerant on Data and Control Input Pins
  • Programmable Transmitter Data and Control Strobe Select (Rising or Falling Edge Strobe)
  • Backward Compatible Configuration Select with FPD-Link
  • Optional Second LVDS Clock for Backward Compatibility w/ FPD-Link
  • Support for Two Additional User-Defined Control Signals in DC Balanced Mode
  • Compatible with ANSI/TIA/EIA-644-1995 LVDS Standard

All trademarks are the property of their respective owners.

The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL data into 8 LVDS (Low Voltage Differential Signalling) data streams. Control signals (VSYNC, HSYNC, DE and two user-defined signals) are sent during blanking intervals. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 672Mbps, providing a total throughput of 5.38Gbps (672 Megabytes per second). Two other modes are also supported. 24-bit color data (single pixel) can be clocked into the transmitter at a maximum rate of 170MHz. In this mode, the transmitter provides single-to-dual pixel conversion, and the output LVDS clock rate is 85MHz maximum. The third mode provides inter-operability with FPD-Link devices.

The LDI chipset is improved over prior generations of FPD-Link devices and offers higher bandwidth support and longer cable drive with three areas of enhancement. To increase bandwidth, the maximum pixel clock rate is increased to 112 (170) MHz and 8 serialized LVDS outputs are provided. Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects. DC balancing on a cycle-to-cycle basis, is also provided to reduce ISI (Inter-Symbol Interference). With pre-emphasis and DC balancing, a low distortion eye-pattern is provided at the receiver end of the cable. A cable deskew capability has been added to deskew long cables of pair-to-pair skew of up to +/−1 LVDS data bit time (up to 80 MHz Clock Rate). These three enhancements allow cables 5+ meters in length to be driven. This chipset is an ideal means to solve EMI and cable size problems for high-resolution flat panel applications. It provides a reliable interface based on LVDS technology that delivers the bandwidth needed for high-resolution panels while maximizing bit times, and keeping clock rates low to reduce EMI and shielding requirements. For more details, please refer to .

The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL data into 8 LVDS (Low Voltage Differential Signalling) data streams. Control signals (VSYNC, HSYNC, DE and two user-defined signals) are sent during blanking intervals. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 672Mbps, providing a total throughput of 5.38Gbps (672 Megabytes per second). Two other modes are also supported. 24-bit color data (single pixel) can be clocked into the transmitter at a maximum rate of 170MHz. In this mode, the transmitter provides single-to-dual pixel conversion, and the output LVDS clock rate is 85MHz maximum. The third mode provides inter-operability with FPD-Link devices.

The LDI chipset is improved over prior generations of FPD-Link devices and offers higher bandwidth support and longer cable drive with three areas of enhancement. To increase bandwidth, the maximum pixel clock rate is increased to 112 (170) MHz and 8 serialized LVDS outputs are provided. Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects. DC balancing on a cycle-to-cycle basis, is also provided to reduce ISI (Inter-Symbol Interference). With pre-emphasis and DC balancing, a low distortion eye-pattern is provided at the receiver end of the cable. A cable deskew capability has been added to deskew long cables of pair-to-pair skew of up to +/−1 LVDS data bit time (up to 80 MHz Clock Rate). These three enhancements allow cables 5+ meters in length to be driven. This chipset is an ideal means to solve EMI and cable size problems for high-resolution flat panel applications. It provides a reliable interface based on LVDS technology that delivers the bandwidth needed for high-resolution panels while maximizing bit times, and keeping clock rates low to reduce EMI and shielding requirements. For more details, please refer to .

Herunterladen Video mit Transkript ansehen Video

Technische Dokumentation

star =Von TI ausgewählte Top-Empfehlungen für dieses Produkt
Keine Ergebnisse gefunden. Bitte geben Sie einen anderen Begriff ein und versuchen Sie es erneut.
Alle anzeigen 9
Typ Titel Datum
* Data sheet DS90C387/DS90CF388 Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA datasheet (Rev. H) 17 Apr 2013
Application note High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 09 Nov 2018
Application note How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) 29 Jun 2018
Application note AN-1032 An Introduction to FPD-Link (Rev. C) 08 Aug 2017
User guide LDI Demonstration Kit User Guide (LVDS Display Interface) Introduction (Rev. A) 01 Apr 2014
Application note TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map 15 Mai 2004
Application note AN-1056 STN Application Using FPD-Link 14 Mai 2004
Application note AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines 14 Mai 2004
Application note LVDS goes the distance! 17 Feb 2003

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Simulationsmodell

DS90CF388 IBIS Model

SNLM052.ZIP (14 KB) - IBIS Model
Simulationstool

PSPICE-FOR-TI — PSpice® für TI Design-und Simulationstool

PSpice® für TI ist eine Design- und Simulationsumgebung, welche Sie dabei unterstützt, die Funktionalität analoger Schaltungen zu evaluieren. Diese voll ausgestattete Design- und Simulationssuite verwendet eine analoge Analyse-Engine von Cadence®. PSpice für TI ist kostenlos erhältlich und (...)
Simulationstool

TINA-TI — SPICE-basiertes analoges Simulationsprogramm

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Benutzerhandbuch: PDF
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
QFP (NEZ) 100 Ultra Librarian

Bestellen & Qualität

Beinhaltete Information:
  • RoHS
  • REACH
  • Bausteinkennzeichnung
  • Blei-Finish/Ball-Material
  • MSL-Rating / Spitzenrückfluss
  • MTBF-/FIT-Schätzungen
  • Materialinhalt
  • Qualifikationszusammenfassung
  • Kontinuierliches Zuverlässigkeitsmonitoring
Beinhaltete Information:
  • Werksstandort
  • Montagestandort

Support und Schulungen

TI E2E™-Foren mit technischem Support von TI-Ingenieuren

Inhalte werden ohne Gewähr von TI und der Community bereitgestellt. Sie stellen keine Spezifikationen von TI dar. Siehe Nutzungsbedingungen.

Bei Fragen zu den Themen Qualität, Gehäuse oder Bestellung von TI-Produkten siehe TI-Support. ​​​​​​​​​​​​​​

Videos