SN65LVDS16

Name: SN65LVDS16
Brand: TI
SKU: SN65LVDS16
Price: 2.104 USD

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Datenblatt

document-pdfAcrobat 2.5-V/3.3-V Oscillator Gain Stage/Buffers datasheet (Rev. B) (Englisch)

SN65LVDS16

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Datenblatt

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Produktdetails

Function

Buffer, Translator

Protocols

LVDS, LVPECL

Number of transmitters

1

Number of receivers

1

Supply voltage (V)

2.5, 3.3

Signaling rate (Mbps)

4000

Input signal

Single-ended

Output signal

LVDS

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Function

Buffer, Translator

Protocols

LVDS, LVPECL

Number of transmitters

1

Number of receivers

1

Supply voltage (V)

2.5, 3.3

Signaling rate (Mbps)

4000

Input signal

Single-ended

Output signal

LVDS

Rating

Catalog

Operating temperature range (°C)

-40 to 85

WSON (DRF)

8

4 mm² 2 x 2

Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs
Clock Rates to 2 GHz
- 140-ps Output Transition Times
- 0.11 ps Typical Intrinsic Phase Jitter
- Less than 630 ps Propagation Delay Times
2.5-V or 3.3-V Supply Operation
2-mm × 2-mm Small-Outline No-Lead Package
APPLICATIONS
- PECL-to-LVDS Translation
- Clock Signal Amplification

Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs
Clock Rates to 2 GHz
- 140-ps Output Transition Times
- 0.11 ps Typical Intrinsic Phase Jitter
- Less than 630 ps Propagation Delay Times
2.5-V or 3.3-V Supply Operation
2-mm × 2-mm Small-Outline No-Lead Package
APPLICATIONS
- PECL-to-LVDS Translation
- Clock Signal Amplification

These four devices are high-frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx16) and fully differential inputs on the SN65LVx17.

The SN65LVx16 provides the user a Gain Control (GC) for controlling the Q output from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to V_CC. (When left open, the Q output defaults to 575 mV.) The Q on the SN65LVx17 defaults to 575 mV as well.

Both devices provide a voltage reference (V_BB) of typically 1.35 V below V_CC for use in receiving single-ended PECL input signals. When not used, V_BB should be unconnected or open.

All devices are characterized for operation from -40°C to 85°C.

These four devices are high-frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on the SN65LVx16) and fully differential inputs on the SN65LVx17.

The SN65LVx16 provides the user a Gain Control (GC) for controlling the Q output from 300 mV to 860 mV either by leaving it open (NC), grounded, or tied to V_CC. (When left open, the Q output defaults to 575 mV.) The Q on the SN65LVx17 defaults to 575 mV as well.

Both devices provide a voltage reference (V_BB) of typically 1.35 V below V_CC for use in receiving single-ended PECL input signals. When not used, V_BB should be unconnected or open.

All devices are characterized for operation from -40°C to 85°C.

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	Typ	Titel		Datum
*	Data sheet	2.5-V/3.3-V Oscillator Gain Stage/Buffers datasheet (Rev. B)		18 Nov 2005

SN65LVDS16

Oszillator-Verstärkungsstufe/Puffer, 2,5/3,3 V, mit Aktivierung

SN65LVDS16

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