인터페이스 이더넷 IC 이더넷 PHY

기가비트 10/100/1000 PHYTER V 이더넷 물리적 계층 트랜시버

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DP83865은(는) 단종 과정에 있습니다.
이 제품은 단종이 진행 중인 제품입니다. 새로운 설계는 대체 제품을 고려해야 합니다.
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비교 대상 장치와 유사한 기능
DP83867E 활성 SGMII를 지원하는 확장된 온도, 견고한 저지연 기가비트 이더넷 PHY 트랜시버 The DP83867E requires less than half the power of the DP83865 and has higher temperature range.

제품 상세 정보

Datarate (Mbps) 10/100/1000 Interface type GMII, MII, RGMII Number of ports Single Rating Catalog Supply voltage (V) 1.8 Operating temperature range (°C) 0 to 70 Number of LEDs 5 ESD HBM (kV) 6
Datarate (Mbps) 10/100/1000 Interface type GMII, MII, RGMII Number of ports Single Rating Catalog Supply voltage (V) 1.8 Operating temperature range (°C) 0 to 70 Number of LEDs 5 ESD HBM (kV) 6
QFP (NND) 128 399.04 mm² 23.2 x 17.2
  • Ultra low power consumption typically 1.1 watt
  • Fully compliant with IEEE 802.3 10BASE-T, 100BASE-TX and 1000BASE-T specifications
  • Integrated PMD sublayer featuring adaptive equalization and baseline wander compensation according to ANSI X3.T12
  • 3.3V or 2.5V MAC interfaces:
  • IEEE 802.3u MII
  • IEEE 802.3z GMII
  • RGMII version 1.3
  • User programmable GMII pin ordering
  • IEEE 802.3u Auto-Negotiation and Parallel Detection
  • Fully Auto-Negotiates between 1000 Mb/s, 100 Mb/s, and 10 Mb/s full duplex and half duplex devices
  • Speed Fallback mode to achieve quality link
  • Cable length estimator
  • LED support for activity, full / half duplex, link1000, link100 and link10, user programmable (manual on/off), or reduced LED mode
  • Supports 25 MHz operation with crystal or oscillator.
  • Requires only two power supplies, 1.8V (core and analog) and 2.5V (analog and I/O). 3.3V is supported as an alternative supply for I/O voltage
  • User programable interrupt
  • Supports Auto-MDIX at 10, 100 and 1000 Mb/s
  • Supports JTAG (IEEE1149.1)
  • 128-pin PQFP package (14mm x 20mm)

  • Ultra low power consumption typically 1.1 watt
  • Fully compliant with IEEE 802.3 10BASE-T, 100BASE-TX and 1000BASE-T specifications
  • Integrated PMD sublayer featuring adaptive equalization and baseline wander compensation according to ANSI X3.T12
  • 3.3V or 2.5V MAC interfaces:
  • IEEE 802.3u MII
  • IEEE 802.3z GMII
  • RGMII version 1.3
  • User programmable GMII pin ordering
  • IEEE 802.3u Auto-Negotiation and Parallel Detection
  • Fully Auto-Negotiates between 1000 Mb/s, 100 Mb/s, and 10 Mb/s full duplex and half duplex devices
  • Speed Fallback mode to achieve quality link
  • Cable length estimator
  • LED support for activity, full / half duplex, link1000, link100 and link10, user programmable (manual on/off), or reduced LED mode
  • Supports 25 MHz operation with crystal or oscillator.
  • Requires only two power supplies, 1.8V (core and analog) and 2.5V (analog and I/O). 3.3V is supported as an alternative supply for I/O voltage
  • User programable interrupt
  • Supports Auto-MDIX at 10, 100 and 1000 Mb/s
  • Supports JTAG (IEEE1149.1)
  • 128-pin PQFP package (14mm x 20mm)

The DP83865 is a fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-T, 100BASE-TX and 1000BASE-T Ethernet protocols.

The DP83865 is an ultra low power version of the DP83861 and DP83891. It uses advanced 0.18 um, 1.8 V CMOS technology, fabricated at National Semiconductors South Portland, Maine facility.

The DP83865 is designed for easy implementation of 10/100/1000 Mb/s Ethernet LANs. It interfaces directly to Twisted Pair media via an external transformer. This device interfaces directly to the MAC layer through the IEEE 802.3u Standard Media Independent Interface (MII), the IEEE 802.3z Gigabit Media Independent Interface (GMII), or Reduced GMII (RGMII).

The DP83865 is a fourth generation Gigabit PHY with field proven architecture and performance. Its robust performance ensures drop-in replacement of existing 10/100 Mbps equipment with ten to one hundred times the performance using the existing networking infrastructure.


The DP83865 is a fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-T, 100BASE-TX and 1000BASE-T Ethernet protocols.

The DP83865 is an ultra low power version of the DP83861 and DP83891. It uses advanced 0.18 um, 1.8 V CMOS technology, fabricated at National Semiconductors South Portland, Maine facility.

The DP83865 is designed for easy implementation of 10/100/1000 Mb/s Ethernet LANs. It interfaces directly to Twisted Pair media via an external transformer. This device interfaces directly to the MAC layer through the IEEE 802.3u Standard Media Independent Interface (MII), the IEEE 802.3z Gigabit Media Independent Interface (GMII), or Reduced GMII (RGMII).

The DP83865 is a fourth generation Gigabit PHY with field proven architecture and performance. Its robust performance ensures drop-in replacement of existing 10/100 Mbps equipment with ten to one hundred times the performance using the existing networking infrastructure.


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유형 직함 날짜
* Data sheet DP83865 Gig PHYTER V 10/100/1000 Ethernet Physical Layer datasheet (Rev. B) 2007/12/11

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치