인터페이스 이더넷 IC 이더넷 리타이머, 리드라이버 및 멀티플렉서 버퍼

DS125DF1610

활성

9.8~12.5Gbps 16채널 리타이머

제품 상세 정보

Type Retimer Mux Number of channels 16 Input compatibility AC-coupling, CML Speed (max) (Gbpp) 12.5 Protocols 10G-SR/LR, 40G-SR4/LR4, CPRI, General purpose, Infiniband, Interlaken Operating temperature range (°C) -40 to 85
Type Retimer Mux Number of channels 16 Input compatibility AC-coupling, CML Speed (max) (Gbpp) 12.5 Protocols 10G-SR/LR, 40G-SR4/LR4, CPRI, General purpose, Infiniband, Interlaken Operating temperature range (°C) -40 to 85
FCBGA (ABB) 196 225 mm² 15 x 15
  • Pin-Compatible Family
    • DS150DF1610: 12.5 to 15 G
    • DS125DF1610: 9.8 to 12.5 G
    • DS110DF1610: 8.5 to 11.3 G
  • 4x4 Analog Cross Point Switch for Each Quad
  • Fully Adaptive CTLE
  • Self tuning DFE, with Optional Continuous Adaption
  • Configurable VGA
  • Adjustable Transmit VOD
  • Adjustable 3-tap Transmit FIR Filter
  • On-chip AC Coupling on Receive Inputs
  • Locks to Half/Quarter/Eighth Data Rates for Legacy Support
  • On-chip Eye Monitor(EOM), PRBS Checker, Pattern Generator
  • Supports JTAG Boundary Scan
  • Programmable Output Polarity Inversion
  • Input Signal Detection, CDR Lock Detection
  • Single 2.5 V ±5% Power Supply
  • SMBus Based Register Configuration
  • Optional EEPROM Configuration
  • 15 mm × 15 mm, 196-pin FCBGA Package
  • Operating Temp Range : –40°C to +85°C
  • Pin-Compatible Family
    • DS150DF1610: 12.5 to 15 G
    • DS125DF1610: 9.8 to 12.5 G
    • DS110DF1610: 8.5 to 11.3 G
  • 4x4 Analog Cross Point Switch for Each Quad
  • Fully Adaptive CTLE
  • Self tuning DFE, with Optional Continuous Adaption
  • Configurable VGA
  • Adjustable Transmit VOD
  • Adjustable 3-tap Transmit FIR Filter
  • On-chip AC Coupling on Receive Inputs
  • Locks to Half/Quarter/Eighth Data Rates for Legacy Support
  • On-chip Eye Monitor(EOM), PRBS Checker, Pattern Generator
  • Supports JTAG Boundary Scan
  • Programmable Output Polarity Inversion
  • Input Signal Detection, CDR Lock Detection
  • Single 2.5 V ±5% Power Supply
  • SMBus Based Register Configuration
  • Optional EEPROM Configuration
  • 15 mm × 15 mm, 196-pin FCBGA Package
  • Operating Temp Range : –40°C to +85°C

The DS125DF1610 is a sixteen-channel multi-rate retimer with integrated signal conditioning features. The device includes a fully adaptive Continuous Time Linear Equalizer (CTLE), Decision Feedback Equalizer (DFE), clock and data recovery (CDR), and a transmit FIR filter to enhance the reach and robustness over long, lossy, crosstalk impaired high speed serial links to achieve BER < 1×10-15.

Each channel of the DS125DF1610 independently locks to serial data at 9.8 to 12.5 Gbps and the divide by 2, 4 and 8 sub-multiples. A simple external oscillator (±100ppm) that is synchronous or asynchronous with the incoming data stream is used as a reference clock. Integrated 4x4 cross point switches allow for full non-blocking routing or broadcasting within each quad of the DS125DF1610.

Programmable transmit FIR filter offers control of the pre-cursor, main tap and post-cursor for transmit equalization. The fully adaptive receive equalization (CTLE and DFE) enables longer distance transmission in lossy copper interconnects and backplanes with multiple connectors.

A non-disruptive mission mode eye-monitor feature allows link monitoring internal to the receiver. The built-in PRBS generator and checker compliment the internal diagnostic features to complete standalone BERT measurements. Built-in JTAG enables manufacturing tests.

The DS125DF1610 is a sixteen-channel multi-rate retimer with integrated signal conditioning features. The device includes a fully adaptive Continuous Time Linear Equalizer (CTLE), Decision Feedback Equalizer (DFE), clock and data recovery (CDR), and a transmit FIR filter to enhance the reach and robustness over long, lossy, crosstalk impaired high speed serial links to achieve BER < 1×10-15.

Each channel of the DS125DF1610 independently locks to serial data at 9.8 to 12.5 Gbps and the divide by 2, 4 and 8 sub-multiples. A simple external oscillator (±100ppm) that is synchronous or asynchronous with the incoming data stream is used as a reference clock. Integrated 4x4 cross point switches allow for full non-blocking routing or broadcasting within each quad of the DS125DF1610.

Programmable transmit FIR filter offers control of the pre-cursor, main tap and post-cursor for transmit equalization. The fully adaptive receive equalization (CTLE and DFE) enables longer distance transmission in lossy copper interconnects and backplanes with multiple connectors.

A non-disruptive mission mode eye-monitor feature allows link monitoring internal to the receiver. The built-in PRBS generator and checker compliment the internal diagnostic features to complete standalone BERT measurements. Built-in JTAG enables manufacturing tests.

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기술 자료

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7개 모두 보기
유형 직함 날짜
* Data sheet DS125DF1610 9.8 to 12.5 Gbps 16-Channel Retimer datasheet (Rev. B) PDF | HTML 2017/01/13
Application note Extend reach with Ethernet Redrivers and Retimers for 10G-12.5G Applications (Rev. A) 2023/01/31
EVM User's guide DS125DF1610EVM User's Guide (Rev. B) 2018/09/20
Technical article Eye doctor: Reflections and how to deal with them in high-speed systems PDF | HTML 2016/09/08
Analog Design Journal Green box testing: A method for optimizing high-speed serial links 2016/07/21
Application note Understanding EEPROM Programming for 10G to 12.5G Retimers 2016/01/13
Application note Selecting TI SigCon Devices for SFF-8431 SFP+ Applications 2014/05/06

설계 및 개발

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평가 보드

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The DS125DF1610EVM allows for easy evaluation of the DS125DF1610.  Users are required to supply power and high speed traffic to the EVM via the SMA connectors. A low cost on board oscillator provides a reference clock for the DS125DF1610’s PPM counter, so external clocking equipment is not (...)

사용 설명서: PDF
TI.com에서 구매 불가
시뮬레이션 모델

DS125DF1610 IBIS-AMI Model

SLNM008.ZIP (28704 KB) - IBIS-AMI Model
시뮬레이션 툴

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TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
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사용 설명서: PDF
레퍼런스 디자인

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This reference design is a 12-Gbps low-cost bit error tester (BERT) capable of generating and checking up to 8 channels of pseudo-random binary sequences (PRBS). This validated design is a convenient way to generate multi-channels high speed serial bit streams of up to 12-Gbps, and checking (...)
Design guide: PDF
회로도: PDF
패키지 CAD 기호, 풋프린트 및 3D 모델
FCBGA (ABB) 196 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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