DS125DF410
- Each Channel Independently Locks to Data Rates from 9.8 to 12.5 Gbps and Submultiples
- Fast Lock Operation Based on Protocol-Select Mode
- Low Latency (~300ps)
- Adaptive Equalization up to 34-dB Boost at 5 GHz
- Adjustable Transmit VOD: 600 to 1300 mVp-p
- Adjustable Transmit De-emphasis to –15 dB
- Typical Power Dissipation (EQ+DFE+CDR+DE): 180 mW/Channel
- Programmable Output Polarity Inversion
- Input Signal Detection, CDR Lock Detection/Indicator
- On-Chip Eye Monitor (EOM), PRBS Generator
- Single 2.5-V ± 5% Power Supply
- SMBus/EEPROM Configuration Modes
- Operating Temperature Range of –40 to 85°C
- WQFN 48-Pin 7-mm x 7-mm Package
- Easy Pin Compatible Upgrade Between Repeater and Retimers
- DS100RT410 (EQ+CDR+DE): 10.3125 Gbps
- DS100DF410 (EQ+DFE+CDR+DE): 10.3125 Gbps
- DS110RT410 (EQ+CDR+DE): 8.5–11.3 Gbps
- DS110DF410 (EQ+DFE+CDR+DE): 8.5–11.3 Gbps
- DS125RT410 (EQ+CDR+DE): 9.8–12.5 Gbps
- DS125DF410 (EQ+DFE+CDR+DE): 9.8–12.5 Gbps
- DS100BR410 (EQ+DE): Up to 10.3125 Gbps
The DS125DF410 is four channel retimer with integrated signal conditioning. The device includes a fully adaptive Continuous-Time Linear Equalizer (CTLE), self calibrating 5-tap Decision Feedback Equalizer (DFE), Clock and Data Recovery (CDR), and transmit De-Emphasis (DE) driver to enable data transmission over long, lossy and crosstalk-impaired highspeed serial links to achieve BER < 1×10-15.
Each channel can independently lock to data rate from 9.8 to 12.5 Gbps, and associated sub rates (div by 2, 4 and 8) to support a variety of communication protocols. A 25 MHz crystal oscillator clock is used to speed up the CDR lock process. This clock is not used for training the PLL and does not need to be synchronous with the serial data.
The programmable settings can be applied using the SMBus (I2C) interface, or they can be loaded via an external EEPROM. An on-chip eye monitor and a PRBS generator allow real-time measurement of high-speed serial data for system bring-up or field tuning.
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | DS125DF410 Low Power Multi-Rate Quad Channel Retimer datasheet (Rev. H) | PDF | HTML | 2018/02/27 |
| Application note | Extend reach with Ethernet Redrivers and Retimers for 10G-12.5G Applications (Rev. A) | 2023/01/31 | ||
| Application note | Implementing TI Retimers on 10G ZR and DWDM SFP+ Optical Links | 2019/04/08 | ||
| Application brief | DS110DF111,DS125DF111, DS100DF410, DS110DF410, and DS125DF410 Programming Guide | 2019/03/25 | ||
| EVM User's guide | DS100DF410EVK, DS110DF410EVK, DS125DF410EVM User's Guide (Rev. C) | 2016/06/22 | ||
| Application note | Understanding EEPROM Programming for 10G to 12.5G Retimers | 2016/01/13 | ||
| Application note | Selecting TI SigCon Devices for SFF-8431 SFP+ Applications | 2014/05/06 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
DS125DF410EVM — DS125DF410EVM: 적응형 EQ, CDR 및 DFE를 갖춘 9.8~12.5.5Gbps 4채널 리타이머
The DS125DF410EVM evaluation board lets you examine the advanced signal conditioning capabilities of the DS125DF410 and DS125RT410 devices using SMAs. The board is controlled by a PC using a USB port and the SigCon Architect GUI.
To use the SigCon Architect GUI to control the device, use the (...)
PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®
TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| WQFN (RHS) | 48 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.