인터페이스 기타 인터페이스

DS90C387R

활성

85MHz 듀얼 12비트 이중 펌프 입력 LDI 송신기 VGA/UXGA

제품 상세 정보

Protocols Catalog Rating Catalog Operating temperature range (°C) -10 to 70
Protocols Catalog Rating Catalog Operating temperature range (°C) -10 to 70
QFP (NEZ) 100 256 mm² 16 x 16
  • Complies with Open LDI Specification for
    Digital Display Interfaces
  • 25 to 85MHz Clock Support
  • Supports VGA through UXGA Panel Resolution
  • Up to 4.76Gbps Bandwidth in Dual 24-bit RGB
    In-to-Dual Pixel Out Application
  • Dual 12-bit Double Pumped Input DVO Port
  • Pre-Emphasis Reduces Cable Loading Effects
  • Drives Long, Low Cost Cables
  • DC Balance Data Transmission Provided by
    Transmitter Reduces ISI Distortion
  • Transmitter Rejects Cycle-to-Cycle Jitter
    (±2ns of Input Bit Period)
  • Support both LVTTL and Low Voltage Level
    Input (Capable of 1.0 to 1.8V)
  • Two-Wire Serial Communication Interface
    up to 400 KHz
  • Programmable Input Clock and Control Strobe
    Select
  • Backward Compatible Configuration with
    112MHz LDI and FPD-Link
  • Optional Second LVDS Clock for Backward
    Compatibility with FPD-Link Receivers
  • Compatible with TIA/EIA-644

All trademarks are the property of their respective owners.

  • Complies with Open LDI Specification for
    Digital Display Interfaces
  • 25 to 85MHz Clock Support
  • Supports VGA through UXGA Panel Resolution
  • Up to 4.76Gbps Bandwidth in Dual 24-bit RGB
    In-to-Dual Pixel Out Application
  • Dual 12-bit Double Pumped Input DVO Port
  • Pre-Emphasis Reduces Cable Loading Effects
  • Drives Long, Low Cost Cables
  • DC Balance Data Transmission Provided by
    Transmitter Reduces ISI Distortion
  • Transmitter Rejects Cycle-to-Cycle Jitter
    (±2ns of Input Bit Period)
  • Support both LVTTL and Low Voltage Level
    Input (Capable of 1.0 to 1.8V)
  • Two-Wire Serial Communication Interface
    up to 400 KHz
  • Programmable Input Clock and Control Strobe
    Select
  • Backward Compatible Configuration with
    112MHz LDI and FPD-Link
  • Optional Second LVDS Clock for Backward
    Compatibility with FPD-Link Receivers
  • Compatible with TIA/EIA-644

All trademarks are the property of their respective owners.

The DS90C387R transmitter is designed to support pixel data transmission from a Host to a Flat Panel Display up to UXGA resolution. It is designed to be compatible with Graphics Memory Controller Hub (GMCH) by implementing two data per clock and can be controlled by a two-wire serial communication interface. Two input modes are supported: one port of 12-bit( two data per clock) input for 24-bit RGB, and two ports of 12-bit( two data per clock) input for dual 24-bit RGB( 48-bit total). In both modes, input data will be clocked on both rising and falling edges in LVTTL level operation, or clocked on the cross over of differential clock signals in the low swing operation. Each input data width will be 1/2 of clock cycle. With an input clock at 85MHz and input data at 170Mbps, the maximum transmission rate of each LVDS line is 595Mbps, for a aggregate throughput rate of 2.38Gbps/4.76Gbps. It converts 24/48 bits (Single/Dual Pixel 24-bit color) of data into 4/8 LVDS (Low Voltage Differential Signaling) data streams. DS90C387R can be programmed via the two-wire serial communication interface. The LVDS output pin-out is identical to DS90C387. Thus, this transmitter can be paired up with DS90CF388, receiver of the 112MHz LDI chipset or FPD-Link Receivers in non-DC Balance mode operation which provides GUI/LCD panel/mother board vendors a wide choice of inter-operation with LVDS based TFT panels.

DS90C387R also comes with features that can be found on DS90C387. Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects. DC Balancing on a cycle-to-cycle basis is also provided to reduce ISI (Inter-Symbol Interference), control signals (VSYNC, HSYNC, DE) are sent during blanking intervals. With pre-emphasis and DC Balancing, a low distortion eye-pattern is provided at the receiver end of the cable. These enhancements allow cables 5 to 15+ meters in length to be driven depending on media characteristic and pixel clock speed. Pre-emphasis is available in both the DC Balanced and Non-DC Balanced modes. In the Non-DC Balanced mode backward compatibility with FPD-Link Receivers is obtained.

This chip is an ideal solution to solve EMI and cable size problems for high-resolution flat panel display applications. It provides a reliable industry standard interface based on LVDS technology that delivers the bandwidth needed for high-resolution panels while maximizing bit times, and keeping clock rates low to reduce EMI and shielding requirements. For more details, please refer to the “Applications Information” section of this datasheet.

The DS90C387R transmitter is designed to support pixel data transmission from a Host to a Flat Panel Display up to UXGA resolution. It is designed to be compatible with Graphics Memory Controller Hub (GMCH) by implementing two data per clock and can be controlled by a two-wire serial communication interface. Two input modes are supported: one port of 12-bit( two data per clock) input for 24-bit RGB, and two ports of 12-bit( two data per clock) input for dual 24-bit RGB( 48-bit total). In both modes, input data will be clocked on both rising and falling edges in LVTTL level operation, or clocked on the cross over of differential clock signals in the low swing operation. Each input data width will be 1/2 of clock cycle. With an input clock at 85MHz and input data at 170Mbps, the maximum transmission rate of each LVDS line is 595Mbps, for a aggregate throughput rate of 2.38Gbps/4.76Gbps. It converts 24/48 bits (Single/Dual Pixel 24-bit color) of data into 4/8 LVDS (Low Voltage Differential Signaling) data streams. DS90C387R can be programmed via the two-wire serial communication interface. The LVDS output pin-out is identical to DS90C387. Thus, this transmitter can be paired up with DS90CF388, receiver of the 112MHz LDI chipset or FPD-Link Receivers in non-DC Balance mode operation which provides GUI/LCD panel/mother board vendors a wide choice of inter-operation with LVDS based TFT panels.

DS90C387R also comes with features that can be found on DS90C387. Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects. DC Balancing on a cycle-to-cycle basis is also provided to reduce ISI (Inter-Symbol Interference), control signals (VSYNC, HSYNC, DE) are sent during blanking intervals. With pre-emphasis and DC Balancing, a low distortion eye-pattern is provided at the receiver end of the cable. These enhancements allow cables 5 to 15+ meters in length to be driven depending on media characteristic and pixel clock speed. Pre-emphasis is available in both the DC Balanced and Non-DC Balanced modes. In the Non-DC Balanced mode backward compatibility with FPD-Link Receivers is obtained.

This chip is an ideal solution to solve EMI and cable size problems for high-resolution flat panel display applications. It provides a reliable industry standard interface based on LVDS technology that delivers the bandwidth needed for high-resolution panels while maximizing bit times, and keeping clock rates low to reduce EMI and shielding requirements. For more details, please refer to the “Applications Information” section of this datasheet.

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기술 자료

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8개 모두 보기
유형 직함 날짜
* Data sheet DS90C387R 85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA datasheet (Rev. G) 2014/01/27
Application note High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 2018/11/09
Application note How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) 2018/06/29
Application note AN-1032 An Introduction to FPD-Link (Rev. C) 2017/08/08
Application note TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map 2004/05/15
Application note AN-1056 STN Application Using FPD-Link 2004/05/14
Application note AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines 2004/05/14
Application note LVDS goes the distance! 2003/02/17

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QFP (NEZ) 100 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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