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SCANSTA112

활성

7포트 멀티드롭 IEEE 1149.1(JTAG) 멀티플렉서

제품 상세 정보

Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
NFBGA (NZD) 100 100 mm² 10 x 10 QFP (NEZ) 100 256 mm² 16 x 16
  • True IEEE 1149.1 Hierarchical and Multidrop Addressable Capability
  • The 8 Address Inputs Support up to 249 Unique Slot Addresses, an Interrogation Address, Broadcast Address, and 4 Multi-Cast Group Addresses (Address 000000 is Reserved)
  • 7 IEEE 1149.1-Compatible Configurable Local Scan Ports
  • Bi-directional Backplane and LSP0 Ports are Interchangeable Slave Ports
  • Capable of Ignoring TRST of the Backplane Port when it Becomes the Slave.
  • Stitcher Mode Bypasses Level 1 and 2 Protocols
  • Mode Register0 Allows Local TAPs to be Bypassed, Selected for Insertion into the Scan Chain Individually, or Serially in Groups of Two or Three
  • Transparent Mode can be Enabled with a Single Instruction to Conveniently Buffer the Backplane IEEE 1149.1 Pins to Those on a Single Local Scan Port
  • General Purpose Local Port Pass Through Bits are Useful for Delivering Write Pulses for Flash Programming or Monitoring Device Status.
  • Known Power-Up State
  • TRST on all Local Scan Ports
  • 32-bit TCK Counter
  • 16-bit LFSR Signature Compactor
  • Local TAPs can Become TRI-STATE via the OE Input to Allow an Alternate Test Master to Take Control of the Local TAPs (LSP0-3 have a TRI-STATE Notification Output)
  • 3.0-3.6V VCC Supply Operation
  • Supports Live Insertion/Withdrawal

All trademarks are the property of their respective owners.

  • True IEEE 1149.1 Hierarchical and Multidrop Addressable Capability
  • The 8 Address Inputs Support up to 249 Unique Slot Addresses, an Interrogation Address, Broadcast Address, and 4 Multi-Cast Group Addresses (Address 000000 is Reserved)
  • 7 IEEE 1149.1-Compatible Configurable Local Scan Ports
  • Bi-directional Backplane and LSP0 Ports are Interchangeable Slave Ports
  • Capable of Ignoring TRST of the Backplane Port when it Becomes the Slave.
  • Stitcher Mode Bypasses Level 1 and 2 Protocols
  • Mode Register0 Allows Local TAPs to be Bypassed, Selected for Insertion into the Scan Chain Individually, or Serially in Groups of Two or Three
  • Transparent Mode can be Enabled with a Single Instruction to Conveniently Buffer the Backplane IEEE 1149.1 Pins to Those on a Single Local Scan Port
  • General Purpose Local Port Pass Through Bits are Useful for Delivering Write Pulses for Flash Programming or Monitoring Device Status.
  • Known Power-Up State
  • TRST on all Local Scan Ports
  • 32-bit TCK Counter
  • 16-bit LFSR Signature Compactor
  • Local TAPs can Become TRI-STATE via the OE Input to Allow an Alternate Test Master to Take Control of the Local TAPs (LSP0-3 have a TRI-STATE Notification Output)
  • 3.0-3.6V VCC Supply Operation
  • Supports Live Insertion/Withdrawal

All trademarks are the property of their respective owners.

The SCANSTA112 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules. Each SCANSTA112 supports up to 7 local IEEE1149.1 scan chains which can be accessed individually or combined serially.

Addressing is accomplished by loading the instruction register with a value matching that of the Slot inputs. Backplane and inter-board testing can easily be accomplished by parking the local TAP Controllers in one of the stable TAP Controller states via a Park instruction. The 32-bit TCK counter enables built in self test operations to be performed on one port while other scan chains are simultaneously tested.

The STA112 has a unique feature in that the backplane port and the LSP0 port are bidirectional. They can be configured to alternatively act as the master or slave port so an alternate test master can take control of the entire scan chain network from the LSP0 port while the backplane port becomes a slave.

The SCANSTA112 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules. Each SCANSTA112 supports up to 7 local IEEE1149.1 scan chains which can be accessed individually or combined serially.

Addressing is accomplished by loading the instruction register with a value matching that of the Slot inputs. Backplane and inter-board testing can easily be accomplished by parking the local TAP Controllers in one of the stable TAP Controller states via a Park instruction. The 32-bit TCK counter enables built in self test operations to be performed on one port while other scan chains are simultaneously tested.

The STA112 has a unique feature in that the backplane port and the LSP0 port are bidirectional. They can be configured to alternatively act as the master or slave port so an alternate test master can take control of the entire scan chain network from the LSP0 port while the backplane port becomes a slave.

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기술 자료

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9개 모두 보기
유형 직함 날짜
* Data sheet SCANSTA112 7-Port Multidrop IEEE 1149.1 (JTAG) Multiplexer datasheet (Rev. I) 2013/04/12
Application note AN-1259 SCANSTA112 Designer's Reference (Rev. H) 2013/04/26
Application note AN-1312 SCANSTA111/SCANSTA112 Scan Bridge Timing (Rev. B) 2013/04/26
Application note Simplified Program of Xilinx Devices Using a SCANSTA111/112 JTAG Scan Chain Mux (Rev. C) 2013/04/26
Application note Simplified Programming of Altera FPGAs Using CSANSTA111/112 JTAG Scan Chain Mux (Rev. D) 2013/04/26
More literature SCANSTA112 7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer Evaluation Kit Docume 2012/02/21
Application note SCANSTA112 Quick Reference Guide 2010/01/07
Application note JTAG Advanced Capabilities and System Design 2009/03/19
Application note Partition IEEE 1149.1 SCAN Chains for Manageability! 2003/03/06

설계 및 개발

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지원 소프트웨어

EVF-WORKBENCH-CONVERTER-SW EVF Workbench - Converts JTAG SVF to National’s EVF2 SCAN Format

Graphical User Interface tool for conversion of SVF files to Texas Instrument’s EVF2 embedded file format. Zip file includes readme file, license file, and setup program (1.6MB)
지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
기타 인터페이스
SCANSTA101 저전압 IEEE 1149.1 STA(System Test Access) 마스터 SCANSTA111 향상된 스캔 브리지 멀티드롭 주소 지정 가능 IEEE 1149.1(JTAG) 포트 SCANSTA112 7포트 멀티드롭 IEEE 1149.1(JTAG) 멀티플렉서
시뮬레이션 모델

SCANSTA112 BSDL File (B0 Backplane)

SNLM195.ZIP (3 KB) - BSDL Model
시뮬레이션 모델

SCANSTA112 BSDL File (B1 Backplane)

SNLM196.ZIP (3 KB) - BSDL Model
시뮬레이션 모델

SCANSTA112 IBIS Model

SNLM151.ZIP (5 KB) - IBIS Model
회로도

SCANSTA112EVK Design Package

SNLC004.PDF (88 KB)
시뮬레이션 툴

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
시뮬레이션 툴

TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
사용 설명서: PDF
패키지 CAD 기호, 풋프린트 및 3D 모델
NFBGA (NZD) 100 Ultra Librarian
QFP (NEZ) 100 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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