SN65DSI85-Q1
- Qualified for Automotive Applications
- AEC-Q100 Qualified With the Following Results:
- Device Temperature Grade 2: –40°C to 105°C Ambient Operating Temperature
- Device HBM ESD Classification Level 3A
- Device CDM ESD Classification Level C6
- Implements MIPI D-PHY Version 1.00.00 Physical Layer Front-End and Display Serial Interface (DSI) Version 1.02.00
- Dual-Channel DSI Receiver Configurable for One, Two, Three, or Four D-PHY Data Lanes Per Channel Operating up to 1 Gbps Per Lane
- Supports 18-bpp and 24-bpp DSI Video Packets with RGB666 and RGB888 Formats
- Suitable for 60-fps WQXGA 2560 × 1600 Resolution at 18-bpp and 24-bpp Color, and 60 fps (120 fps Equivalent) WUXGA 1920 × 1200 Resolution With 3D Graphics at 24-bpp Color
- MIPI Front-End Configurable for Single-Channel or Dual-Channel DSI Configurations
- Output Configurable for Single-Link or Dual-Link LVDS
- Supports Dual-Channel DSI ODD or EVEN and LEFT or RIGHT Operating Modes
- Supports Two Single-Channel DSI to Two Single-Link LVDS Operating Mode
- LVDS Output-Clock Range of 25 MHz to 154 MHz in Dual-Link or Single-Link Mode
- LVDS Pixel Clock May be Sourced from Free-Running Continuous D-PHY Clock or External Reference Clock (REFCLK)
- 1.8-V Main VCC Power Supply
- Low Power Features Include SHUTDOWN Mode, Reduced LVDS Output Voltage Swing, Common Mode, and MIPI Ultra-Low Power State (ULPS) Support
- LVDS Channel SWAP, LVDS PIN Order Reverse Feature for Ease of PCB Routing
- Packaged in 64-pin 10 mm × 10 mm HTQFP (PAP) PowerPAD™ IC Package
The SN65DSI85-Q1 DSI-to-LVDS bridge features a dual-channel MIPI D-PHY receiver front-end
configuration with four lanes per channel operating at 1 Gbps per lane and a maximum input bandwidth of 8 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data-stream to an LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a dual-link LVDS, single-link LVDS, or two Single-Link LVDS interfaces with four data lanes per link.
The SN65DSI85-Q1 device is well suited for WQXGA (2560 × 1600) at 60 frames per second (fps), as well as 3D Graphics at WUXGA and True HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bits-per-pixel (bpp). Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.
The SN65DSI85-Q1 device is implemented in a small outline 10 mm × 10 mm HTQFP package with a
0.5-mm pitch, and operates across a temperature range from –40°C to 105°C.
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기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | SN65DSI85-Q1 Automotive Dual-Channel MIPI DSI to Dual-Link LVDS Bridge datasheet (Rev. B) | PDF | HTML | 2018/06/28 |
| Application note | Troubleshooting SN65DSI8x - Tips and Tricks | 2018/08/27 | ||
| EVM User's guide | SN65DSI83, SN65DSI84, and SN65DSI85 EVM User’s Manual and Implementation Guide | 2015/11/17 |
설계 및 개발
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TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램
TIDA-01453 — 차량용 인포테인먼트 헤드 유닛을 위한 MIPI® DSI-ODDI/LVDS 브리지 레퍼런스 설계
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| HTQFP (PAP) | 64 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
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