SN65MLVD204A
- Low-Voltage Differential 30Ω to 55Ω Line Drivers and Receivers for Signaling Rates (1) up to 100Mbps, Clock Frequencies up to 50MHz
- Type-1 Receivers Incorporate 25mV of Hysteresis (SN65MLVD200A, SN65MLVD202A)
- Type-2 Receivers Provide an Offset (100mV) Threshold to Detect Open-Circuit and Idle-Bus Conditions (SN65MLVD204A, SN65MLVD205A)
- Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Data Interchange
- Controlled Driver Output Voltage Transition Times for Improved Signal Quality
- –1V to 3.4V of Common-Mode Voltage Range Allows Data Transfer With 2V of Ground Noise
- Bus Pins High Impedance When Disabled or VCC ≤ 1.5V
- 200Mbps Devices Available (SN65MLVD201, SN65MLVD203, SN65MLVD206, SN65MLVD207)
- Bus Pin ESD Protection Exceeds 8kV
- Packages Available:
- 8-Pin SOIC SN65MLVD200A, SN65MLVD204A
- 14-Pin SOIC SN65MLVD202A, SN65MLVD205A
- Improved Alternatives to the SN65MLVD200, SN65MLVD202A, SN65MLVD204A, and SN65MLVD205A Devices
(1)The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second)
The SN65MLVD20xx devices are multipoint low-voltage differential (M-LVDS) line drivers and receivers that are optimized to operate at signaling rates up to 100 Mbps. All parts comply with the multipoint low-voltage differential signaling (M-LVDS) standard TIA/EIA-899.
The SN65MLVD20xx devices have enhancements over their predecessors. Improved features include controlled slew rate on the driver output to help minimize reflections from unterminated stubs, which results in better signal integrity. Additionally, 8-kV ESD protection on the bus pins for more robustness. The same footprint definition was maintained making for an easy drop-in replacement for a system performance upgrade.
The devices are characterized for operation from –40°C to 85°C.
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | SN65MLVD20xx Multipoint-LVDS Line Driver and Receiver datasheet (Rev. E) | PDF | HTML | 2024/03/01 |
| Application note | An Introduction to M-LVDS and Clock and Data Distribution Applications (Rev. C) | PDF | HTML | 2023/06/22 | |
| Application brief | How Far, How Fast Can You Operate MLVDS? | 2018/08/06 | ||
| Application note | SPI-Based Data Acquisition/Monitor Using the TLC2551 Serial ADC (Rev. A) | 2001/11/20 |
설계 및 개발
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MLVD20XEVM — M-LVDS 평가 모듈
The SN65MLVD203B is a full-duplex transceiver, and the SN65MLVD204B is a half-duplex transceiver.
SN65MLVD2-3EVM — SN65MLVD2-3EVM 평가 모듈
The SN65MLVD2 and SN65MLVD3 are single-channel M-LVDS receivers. These devices are designed in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to250 Mbps. Each receiver channel is controlled by a receive enable (/RE). When /RE = low, (...)
PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®
TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| SOIC (D) | 8 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.