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TLK10002

활성

듀얼 채널 10Gbps 다중 속도 트랜시버

제품 상세 정보

Protocols Catalog Device type Aggregator Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Device type Aggregator Rating Catalog Operating temperature range (°C) -40 to 85
FCBGA (CTR) 144 169 mm² 13 x 13
  • Dual-Channel, 10-Gbps, Multi-Rate Transceiver
  • Supports All CPRI and OBSAI Data Rates From 1 Gbps to 10 Gbps
  • Integrated Latency Measurement Function, Accuracy up to 814 ps
  • Supports SERDES Operation With up to 10-Gbps Data Rate on the High-Speed Side and up to 5G bps on the Low-Speed Side
  • Differential CML I/Os on Both High-Speed and Low-Speed Sides
  • Shared or Independent Reference Clock Per Channel
  • Loopback Capability on Both High-Speed and Low-Speed Sides, OBSAI Compliant
  • Supports Data Retime Operation
  • Supports PRBS 27-1, 223-1 and 231-1 and High-Frequency, Low-Frequency, Mixed-Frequency, and CRPAT Long and Short Pattern Generation and Verification
  • Two Power Supplies: 1-V Core, and 1.5-V or 1.8-V I/O
  • Transmit De-Emphasis and Receive Adaptive Equalization to Allow Extended Backplane or Cable Reach on Both High-Speed and Low-Speed Sides
  • Programmable Transmit Output Swing on Both High-Speed and Low-Speed Sides.
  • Minimum Receiver Differential Input Threshold of 100 mVpp
  • Loss-of-Signal (LOS) Detection
  • Interface to Backplanes, Passive and Active Copper Cables, or SFP/SFP+ Optical Modules
  • Hot Plug Protection
  • JTAG; IEEE 1149.1 Test Interface
  • MDIO; IEEE 802.3 Clause-22 Support
  • 65-nm Advanced CMOS Technology
  • Industrial Ambient Operating Temperature (–40°C to 85°C) at Full Rate
  • Power Consumption: 1.6 W Typical
  • Device Package: 13-mm × 13-mm, 144-pin PBGA, 1-mm Ball-Pitch
  • Dual-Channel, 10-Gbps, Multi-Rate Transceiver
  • Supports All CPRI and OBSAI Data Rates From 1 Gbps to 10 Gbps
  • Integrated Latency Measurement Function, Accuracy up to 814 ps
  • Supports SERDES Operation With up to 10-Gbps Data Rate on the High-Speed Side and up to 5G bps on the Low-Speed Side
  • Differential CML I/Os on Both High-Speed and Low-Speed Sides
  • Shared or Independent Reference Clock Per Channel
  • Loopback Capability on Both High-Speed and Low-Speed Sides, OBSAI Compliant
  • Supports Data Retime Operation
  • Supports PRBS 27-1, 223-1 and 231-1 and High-Frequency, Low-Frequency, Mixed-Frequency, and CRPAT Long and Short Pattern Generation and Verification
  • Two Power Supplies: 1-V Core, and 1.5-V or 1.8-V I/O
  • Transmit De-Emphasis and Receive Adaptive Equalization to Allow Extended Backplane or Cable Reach on Both High-Speed and Low-Speed Sides
  • Programmable Transmit Output Swing on Both High-Speed and Low-Speed Sides.
  • Minimum Receiver Differential Input Threshold of 100 mVpp
  • Loss-of-Signal (LOS) Detection
  • Interface to Backplanes, Passive and Active Copper Cables, or SFP/SFP+ Optical Modules
  • Hot Plug Protection
  • JTAG; IEEE 1149.1 Test Interface
  • MDIO; IEEE 802.3 Clause-22 Support
  • 65-nm Advanced CMOS Technology
  • Industrial Ambient Operating Temperature (–40°C to 85°C) at Full Rate
  • Power Consumption: 1.6 W Typical
  • Device Package: 13-mm × 13-mm, 144-pin PBGA, 1-mm Ball-Pitch

The TLK10002 device is a dual-channel, multi-rate transceiver intended for use in high-speed bidirectional point-to-point data transmission systems. It has special support for the wireless base station Remote Radio Head (RRH) application, but may also be used in other high-speed applications. It supports all the CPRI and OBSAI rates from 1.2288 Gbps to 9.8304 Gbps.

The TLK10002 performs 1:1, 2:1 and 4:1 serialization of the 8B/10B encoded data streams presented on its low-speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high-speed (HS) side outputs. Likewise, the TLK10002 performs 1:1, 1:2 and 1:4 deserialization of 8B/10B encoded data streams presented on its high-speed side data inputs. The deserialized 8B/10B encoded data is presented on the low-speed side outputs. Depending on the serialization or deserialization ratio, the low-speed side data rate can range from 0.5 Gbps to 5 Gbps and the high-speed side data rate can range from 1 Gbps to 10 Gbps. Both low-speed and high-speed side data inputs and outputs are of differential current mode logic (CML) type with integrated termination resistors. In the 1:1 mode, the input can be raw (non-8B/10B encoded) data, allowing for transmission of PRBS data through the device.

The TLK10002 performs data serialization or deserialization and clock extraction as a physical layer interface device. Flexible clocking schemes are provided to support various operations. They include the support for clocking with an externally-jitter-cleaned clock recovered from the high-speed side.

The TLK10002 provides two low-speed side and two high-speed side loopback modes for self-test and system diagnostic purposes.

The TLK10002 has built-in pattern generation and verification to help in system tests. The low speed side supports generation and verification of PRBS 27-1, 223-1, and 231-1 patterns. In addition to those PRBS patterns, the high-speed side supports High, Low, Mixed, and CRPAT long and short pattern generation and verification.

The TLK10002 has an integrated loss-of-signal (LOS) detection function on both high-speed and low-speed sides. LOS is asserted in conditions where the input differential voltage swing is less than the LOS assert threshold. The input differential voltage swing must exceed the de-assert threshold for the LOS condition to be cleared.

Lane alignment for each channel is achieved through a proprietary lane alignment scheme implemented on the low-speed side interface. The interfaced upstream link partner device needs to implement the lane alignment scheme for the correct link operation. Normal link operation resumes only after lane alignment is achieved.

The two TLK10002 channels are fully independent. They can be operated with different reference clocks, at different data rates, and with different serialization or deserialization ratios.

The low-speed side of the TLK10002 is ideal for interfacing with an FPGA or ASIC located on the same local physical system. The high-speed side is ideal for interfacing with remote systems through an optical fiber, an electrical cable, or a backplane interface. The TLK10002 supports operation with SFP and SFP+ optical modules.

The TLK10002 device is a dual-channel, multi-rate transceiver intended for use in high-speed bidirectional point-to-point data transmission systems. It has special support for the wireless base station Remote Radio Head (RRH) application, but may also be used in other high-speed applications. It supports all the CPRI and OBSAI rates from 1.2288 Gbps to 9.8304 Gbps.

The TLK10002 performs 1:1, 2:1 and 4:1 serialization of the 8B/10B encoded data streams presented on its low-speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high-speed (HS) side outputs. Likewise, the TLK10002 performs 1:1, 1:2 and 1:4 deserialization of 8B/10B encoded data streams presented on its high-speed side data inputs. The deserialized 8B/10B encoded data is presented on the low-speed side outputs. Depending on the serialization or deserialization ratio, the low-speed side data rate can range from 0.5 Gbps to 5 Gbps and the high-speed side data rate can range from 1 Gbps to 10 Gbps. Both low-speed and high-speed side data inputs and outputs are of differential current mode logic (CML) type with integrated termination resistors. In the 1:1 mode, the input can be raw (non-8B/10B encoded) data, allowing for transmission of PRBS data through the device.

The TLK10002 performs data serialization or deserialization and clock extraction as a physical layer interface device. Flexible clocking schemes are provided to support various operations. They include the support for clocking with an externally-jitter-cleaned clock recovered from the high-speed side.

The TLK10002 provides two low-speed side and two high-speed side loopback modes for self-test and system diagnostic purposes.

The TLK10002 has built-in pattern generation and verification to help in system tests. The low speed side supports generation and verification of PRBS 27-1, 223-1, and 231-1 patterns. In addition to those PRBS patterns, the high-speed side supports High, Low, Mixed, and CRPAT long and short pattern generation and verification.

The TLK10002 has an integrated loss-of-signal (LOS) detection function on both high-speed and low-speed sides. LOS is asserted in conditions where the input differential voltage swing is less than the LOS assert threshold. The input differential voltage swing must exceed the de-assert threshold for the LOS condition to be cleared.

Lane alignment for each channel is achieved through a proprietary lane alignment scheme implemented on the low-speed side interface. The interfaced upstream link partner device needs to implement the lane alignment scheme for the correct link operation. Normal link operation resumes only after lane alignment is achieved.

The two TLK10002 channels are fully independent. They can be operated with different reference clocks, at different data rates, and with different serialization or deserialization ratios.

The low-speed side of the TLK10002 is ideal for interfacing with an FPGA or ASIC located on the same local physical system. The high-speed side is ideal for interfacing with remote systems through an optical fiber, an electrical cable, or a backplane interface. The TLK10002 supports operation with SFP and SFP+ optical modules.

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관심 가지실만한 유사 제품

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비교 대상 장치와 유사한 기능
TLK6002 활성 듀얼 채널 470Mbps~6.25Gbps 다중 속도 트랜시버 Dual Channel serdes support data rates up to 6.25Gbps

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
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5개 모두 보기
유형 직함 날짜
* Data sheet TLK10002 10-Gbps, Dual-Channel, Multi-Rate Transceiver datasheet (Rev. B) PDF | HTML 2016/07/28
Application note Driving the TLK10002 10Gpbs SERDES with the CDCM6208 Clock Generator 2012/12/14
Application note TLK10002 Latency Measurement in Wireless Base Station System 2012/03/13
User guide TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver EVM 2011/05/09
EVM User's guide TLK10002 Dual-Chnl, 10-Gbps, Multi-Rate Transceiver EVM Graphical User Interface 2011/05/07

설계 및 개발

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평가 보드

TLK10002EVM — TLK10002EVM 평가 모듈

Motherboard evaluation module for TLK10002.
사용 설명서: PDF
평가 모듈(EVM)용 GUI

SLLC422 TLK10002 EVM GUI

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
기타 인터페이스
TLK10002 듀얼 채널 10Gbps 다중 속도 트랜시버
하드웨어 개발
평가 보드
TLK10002EVM TLK10002EVM 평가 모듈
시뮬레이션 모델

TLK10002 HSPICE Model

SLLM143.ZIP (9023 KB) - HSpice Model
시뮬레이션 모델

TLK10002 IBIS Model

SLLM144.ZIP (61 KB) - IBIS Model
회로도

TI Lane Align Ref Design v04

SLLC431.ZIP (4947 KB)
시뮬레이션 툴

PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®

TI용 PSpice®는 아날로그 회로의 기능을 평가하는 데 사용되는 설계 및 시뮬레이션 환경입니다. 완전한 기능을 갖춘 이 설계 및 시뮬레이션 제품군은 Cadence®의 아날로그 분석 엔진을 사용합니다. 무료로 제공되는 TI용 PSpice에는 아날로그 및 전력 포트폴리오뿐 아니라 아날로그 행동 모델에 이르기까지 업계에서 가장 방대한 모델 라이브러리 중 하나가 포함되어 있습니다.

TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
시뮬레이션 툴

TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
사용 설명서: PDF
패키지 CAD 기호, 풋프린트 및 3D 모델
FCBGA (CTR) 144 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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지원 및 교육

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