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DSP type 1 C64x DSP (max) (MHz) 400, 500, 600, 700 CPU 32-/64-bit Operating system DSP/BIOS, VLX Ethernet MAC 10/100 Rating Catalog Operating temperature range (°C) 0 to 90
DSP type 1 C64x DSP (max) (MHz) 400, 500, 600, 700 CPU 32-/64-bit Operating system DSP/BIOS, VLX Ethernet MAC 10/100 Rating Catalog Operating temperature range (°C) 0 to 90
BGA (ZDU) 376 529 mm² 23 x 23 NFBGA (ZWT) 361 256 mm² 16 x 16
  • Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!
  • High-Performance Digital Media Processor (DM6435)
    • 2.5-, 2-, 1.67, 1.51-, 1.43-ns Instruction Cycle Time
    • 400-, 500-, 600-, 660-, 700-MHz C64x+™ Clock Rate
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 3200, 4000, 4800, 5280, 5600 MIPS
    • Fully Software-Compatible With C64x
    • Commercial and Automotive (Q or S suffix) Grades
    • Low-Power Device (L suffix)
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2 Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Auto-Focus Module Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2 Increased Orthogonality
    • C64x+ Extensions
      • Compact 16-bit Instructions
      • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 256K-Bit (32K-Byte) L1P Program RAM/Cache [Flexible Allocation]
    • 640K-Bit (80K-Byte) L1D Data RAM/Cache [Flexible Allocation]
    • 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation]
  • Supports Little Endian Mode Only
  • Video Processing Subsystem (VPSS), VPFE Only
    • Front End Provides:
      • CCD and CMOS Imager Interface
      • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
      • Preview Engine for Real-Time Image Processing
      • Glueless Interface to Common Video Decoders
      • Histogram Module
      • Auto-Exposure, Auto-White Balance and Auto-Focus Module
      • Resize Engine
        • Resize Images From 1/4× to 4×
        • Separate Horizontal/Vertical Control
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
      • Supports up to 333-MHz (data rate) bus and interfaces to DDR2-400 SDRAM
    • Asynchronous 8-Bit Wide EMIF (EMIFA) With up to 64M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-Bit-Wide Data)
        • NAND (8-Bit-Wide Data)
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watch Dog Timer
  • Two UARTs (One with RTS and CTS Flow Control)
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Multichannel Buffered Serial Port (McBSP)
    • I2S and TDM
    • AC97 Audio Codec Interface
    • SPI
    • Standard Voice Codec Interface (AIC12)
    • Telecom Interfaces - ST-Bus, H-100
    • 128 Channel Mode
  • Multichannel Audio Serial Port (McASP0)
    • Four Serializers and SPDIF (DIT) Mode
  • 16-Bit Host-Port Interface (HPI)
  • High-End CAN Controller (HECC)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Supports Media Independent Interface (MII)
    • Management Data I/O (MDIO) Module
  • VLYNQ™ Interface (FPGA Interface)
  • Three Pulse Width Modulator (PWM) Outputs
  • On-Chip ROM Bootloader
  • Individual Power-Savings Modes
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
  • Up to 111 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • Packages:
    • 361-Pin Pb-Free PBGA Package (ZWT Suffix), 0.8-mm Ball Pitch
    • 376-Pin Plastic BGA Package (ZDU Suffix), 1.0-mm Ball Pitch
  • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal (-7/-6/-5/-4/-L/-Q6/-5Q/-4Q)
  • 3.3-V and 1.8-V I/O, 1.05-V Internal (-7/-6/-5/-4/-L/-Q5)
  • Applications:
    • Digital Media
  • Networked Media Encode
  • Video Imaging

All trademarks are the property of their respective owners.

  • Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!
  • High-Performance Digital Media Processor (DM6435)
    • 2.5-, 2-, 1.67, 1.51-, 1.43-ns Instruction Cycle Time
    • 400-, 500-, 600-, 660-, 700-MHz C64x+™ Clock Rate
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 3200, 4000, 4800, 5280, 5600 MIPS
    • Fully Software-Compatible With C64x
    • Commercial and Automotive (Q or S suffix) Grades
    • Low-Power Device (L suffix)
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2 Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Auto-Focus Module Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2 Increased Orthogonality
    • C64x+ Extensions
      • Compact 16-bit Instructions
      • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 256K-Bit (32K-Byte) L1P Program RAM/Cache [Flexible Allocation]
    • 640K-Bit (80K-Byte) L1D Data RAM/Cache [Flexible Allocation]
    • 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation]
  • Supports Little Endian Mode Only
  • Video Processing Subsystem (VPSS), VPFE Only
    • Front End Provides:
      • CCD and CMOS Imager Interface
      • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
      • Preview Engine for Real-Time Image Processing
      • Glueless Interface to Common Video Decoders
      • Histogram Module
      • Auto-Exposure, Auto-White Balance and Auto-Focus Module
      • Resize Engine
        • Resize Images From 1/4× to 4×
        • Separate Horizontal/Vertical Control
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
      • Supports up to 333-MHz (data rate) bus and interfaces to DDR2-400 SDRAM
    • Asynchronous 8-Bit Wide EMIF (EMIFA) With up to 64M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-Bit-Wide Data)
        • NAND (8-Bit-Wide Data)
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watch Dog Timer
  • Two UARTs (One with RTS and CTS Flow Control)
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Multichannel Buffered Serial Port (McBSP)
    • I2S and TDM
    • AC97 Audio Codec Interface
    • SPI
    • Standard Voice Codec Interface (AIC12)
    • Telecom Interfaces - ST-Bus, H-100
    • 128 Channel Mode
  • Multichannel Audio Serial Port (McASP0)
    • Four Serializers and SPDIF (DIT) Mode
  • 16-Bit Host-Port Interface (HPI)
  • High-End CAN Controller (HECC)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Supports Media Independent Interface (MII)
    • Management Data I/O (MDIO) Module
  • VLYNQ™ Interface (FPGA Interface)
  • Three Pulse Width Modulator (PWM) Outputs
  • On-Chip ROM Bootloader
  • Individual Power-Savings Modes
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
  • Up to 111 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • Packages:
    • 361-Pin Pb-Free PBGA Package (ZWT Suffix), 0.8-mm Ball Pitch
    • 376-Pin Plastic BGA Package (ZDU Suffix), 1.0-mm Ball Pitch
  • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal (-7/-6/-5/-4/-L/-Q6/-5Q/-4Q)
  • 3.3-V and 1.8-V I/O, 1.05-V Internal (-7/-6/-5/-4/-L/-Q5)
  • Applications:
    • Digital Media
  • Networked Media Encode
  • Video Imaging

All trademarks are the property of their respective owners.

The TMS320C64x+™ DSPs (including the TMS320DM6435 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM6435 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units–two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The DM6435 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6435 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 640K-bit memory space–384K-bit of which is mapped memory and 256K-bit of which can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: a configurable video port (VPFE); a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; a multichannel buffered serial port (McBSP); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (HPI); up to 111-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 2 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; 1 high-end controller area network (CAN) controller [HECC]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The DM6435 device includes a Video Processing Subsystem (VPSS) with a configurable video/imaging front-end input peripheral used for video capture.

The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine (Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or CCD and converts from an RGB Bayer Pattern to YUV422. The Histogram and H3A modules provide statistical information on the raw color data for use by the DM6435. The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM6435 and the network. The DM6435 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system.

The I2C and VLYNQ ports allow DM6435 to easily control peripheral devices and/or communicate with host processors.

The high-end controller area network (CAN) controller [HECC] module provides a network protocol in a harsh environment to communicate serially with other controllers, typically in automotive applications.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The DM6435 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

The TMS320C64x+™ DSPs (including the TMS320DM6435 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM6435 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units–two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The DM6435 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6435 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 640K-bit memory space–384K-bit of which is mapped memory and 256K-bit of which can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: a configurable video port (VPFE); a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; a multichannel buffered serial port (McBSP); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (HPI); up to 111-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 2 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; 1 high-end controller area network (CAN) controller [HECC]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The DM6435 device includes a Video Processing Subsystem (VPSS) with a configurable video/imaging front-end input peripheral used for video capture.

The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine (Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or CCD and converts from an RGB Bayer Pattern to YUV422. The Histogram and H3A modules provide statistical information on the raw color data for use by the DM6435. The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM6435 and the network. The DM6435 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system.

The I2C and VLYNQ ports allow DM6435 to easily control peripheral devices and/or communicate with host processors.

The high-end controller area network (CAN) controller [HECC] module provides a network protocol in a harsh environment to communicate serially with other controllers, typically in automotive applications.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The DM6435 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

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56개 모두 보기
유형 직함 날짜
* Data sheet TMS320DM6435 Digital Media Processor datasheet (Rev. C) 2008/06/06
* Errata TMS320DM6437/35/33/31 DMP Silicon Errata (Revs. 1.3 1.2 1.1 & 1.0) (Rev. E) 2011/08/12
Application note Plastic Ball Grid Array [PBGA] Application Note (Rev. B) 2015/08/13
User guide TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W) 2012/08/21
User guide TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U) 2012/08/21
Application note Using the TMS320DM643x Bootloader (Rev. E) 2012/03/23
Application note Introduction to TMS320C6000 DSP Optimization 2011/10/06
User guide TMS320C6000 Programmer's Guide (Rev. K) 2011/07/11
User guide TMS320DM643x DMP Inter-Integrated Circuit (I2C) Module User's Guide (Rev. E) 2011/03/25
User guide TMS320DM643x DMP DDR2 Memory Controller User's Guide (Rev. C) 2011/01/12
User guide TMS320DM643x DMP EMAC/MDIO User's Guide (Rev. C) 2010/12/23
User guide TMS320DM643x DMP Video Processing Front End (VPFE) User's Guide (Rev. D) 2010/08/25
User guide TMS320DM643x DMP Pulse-Width Modulator (PWM) User's Guide (Rev. B) 2010/08/05
User guide TMS320C64x+ DSP Megamodule Reference Guide (Rev. K) 2010/08/03
User guide TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) 2010/07/30
Application note TMS320DM643x Power Consumption Summary (Rev. C) 2010/05/10
User guide TMS320C6000 Assembly Language Tools v 7.0 User's Guide (Rev. S) 2010/03/18
User guide TMS320C6000 Optimizing Compiler v 7.0 User's Guide (Rev. Q) 2010/03/18
User guide TMS320DM643x DMP Universal Asynchronous Receiver/Transmitter (UART) UG (Rev. C) 2009/12/16
Application note Common Object File Format (COFF) 2009/04/15
User guide TMS320DM643x DMP Asynchronous External Memory Interface (EMIF) UG (Rev. B) 2009/02/24
User guide TMS320C64x+ DSP Cache User's Guide (Rev. B) 2009/02/11
Application note 12Vin DM643x Power using Integrated-FET DC/DC Converters and LDO 2008/10/09
Application note 5Vin DM643x Power using DC/DC Controllers and LDO 2008/10/09
Application note 5Vin DM643x Power using Integrated-FET DC/DC Converters and LDO 2008/10/09
Application note 5Vin DM643x Power using a PMIC (Multi-output DC/DC Converter) 2008/10/09
Application note Migrating from EDMA v2.0 to EDMA v3.0 TMS320C64X DSP (Rev. A) 2008/08/21
Application note Understanding the Davinci Preview Engine (Rev. A) 2008/07/23
Application note Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A) 2008/07/17
Application note Understanding the Davinci Resizer (Rev. B) 2008/07/17
User guide TMS320DM643x DMP Host Port Interface (HPI) User's Guide (Rev. D) 2008/07/16
Application note Implementing DDR2 PCB Layout on the TMS320DM643x DMSoC (Rev. A) 2008/06/26
Application note How to Use the EDMA3 Driver on a TMS320DM643x Device (Rev. A) 2008/06/16
User guide TMS320C6000 Assembly Language Tools v 6.1 User's Guide (Rev. Q) 2008/05/15
User guide TMS320C6000 Optimizing Compiler v 6.1 User's Guide (Rev. O) 2008/05/15
User guide TMS320C64x+ DSP Image/Video Processing Library (v2.0) Programmer's Reference (Rev. A) 2008/05/05
User guide TMS320DM643x DMP General-Purpose Input/Output (GPIO) User's Guide (Rev. B) 2008/03/18
User guide TMS320DM643x DMP Multichannel Audio Serial Port (McASP) User's Guide (Rev. D) 2008/03/13
User guide TMS320C64x+ DSP Little-Endian Library Programmer's Reference (Rev. B) 2008/03/06
User guide TMS320DM643x DMP Enhanced DMA (EDMA) Controller User's Guide (Rev. A) 2008/03/03
User guide TMS320DM643x DMP DSP Subsystem Reference Guide (Rev. E) 2008/02/05
Application note How to Use the VPBE and VPFE Driver on the TMS320DM643x Devices (Rev. A) 2007/11/14
User guide TMS320DM643x DMP VLYNQ Port User's Guide (Rev. B) 2007/09/20
User guide TMS320DM643x DMP Multichannel Buffered Serial Port (McBSP) User's Guide (Rev. C) 2007/09/17
Application note TMS320DM643x Pin Multiplexing Utility 2007/07/06
User guide TMS320DM643x DMP Peripherals Overview Reference Guide (Rev. A) 2007/06/25
Application note Thermal Considerations for the DM64xx, DM64x, and C6000 Devices 2007/05/20
User guide TMS320DM643x DMP High-End CAN Controller (HECC) User's Guide (Rev. A) 2007/05/15
Product overview TMS320C6000 DSP TCP/IP Stack Software (Rev. C) 2007/04/04
Product overview DaVinci Technology - Digital Video Innovation Product Bulletin (Rev. D) 2007/02/13
More literature Overview of DaVinci™ TMS320DM643x Digital Media Portfolio (Rev. B) 2007/02/13
Application note DaVinci Technology Background and Specifications (Rev. A) 2007/01/04
User guide TMS320DM643x DMP 64-Bit Timer User's Guide 2006/12/18
User guide TMS320C64x+ DSP Big-Endian Library Programmer's Reference 2006/03/10
User guide TMS320C64x+ Image/Video Processing Library Programmer's Reference 2006/03/10
Application note Migrating from TMS320C64x to TMS320C64x+ (Rev. A) 2005/10/20

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디버그 프로브

TMDSEMU200-U — XDS200 USB 디버그 프로브

XDS200은 TI 임베디드 디바이스 디버깅에 사용되는 디버그 프로브(에뮬레이터)입니다. XDS200은 저렴한 XDS110 및 고성능 XDS560v2에 비해 저렴한 비용으로 우수한 성능을 균형 있게 제공합니다. 단일 포드에서 광범위한 표준(IEEE1149.1, IEEE1149.7, SWD)을 지원합니다. 모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 Arm® 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 코어 추적의 경우 XDS560v2 PRO TRACE가 (...)

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디버그 프로브

TMDSEMU560V2STM-U — XDS560v2 시스템 추적 USB 디버그 프로브

XDS560v2는 디버그 프로브의 XDS560™ 제품군 중 최고의 성능을 가진 제품으로, 기존의 JTAG 표준(IEEE1149.1)과 cJTAG(IEEE1149.7)를 모두 지원합니다. SWD(직렬 와이어 디버그)는 지원하지 않습니다.

모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 ARM 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 추적의 경우 XDS560v2 PRO TRACE가 필요합니다.

XDS560v2는 MIPI HSPT 60핀 커넥터(TI 14핀, (...)

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디버그 프로브

TMDSEMU560V2STM-UE — XDS560v2 시스템 추적 USB 및 이더넷 디버그 프로브

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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애플리케이션 소프트웨어 및 프레임워크

TMDMFP — 멀티미디어 프레임워크 제품(MFP) - 코덱 엔진, 프레임워크 구성 요소 및 XDAIS

Multimedia Framework Products (MFP)

A major advantage of programmable signal processors over fixed-function devices is their ability to accelerate multiple multimedia functions and provide flexible environments to enable user customization. However, sharing scarce embedded hardware resources between (...)

사용 설명서: PDF
드라이버 또는 라이브러리

SPRC122 C62x/C64x Fast Run-Time Support Library

The C62x/64x FastRTS Library is an optimized, floating-point function library for C programmers using either TMS320C62x or TMS320C64x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By replacing the current (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
DSP(디지털 신호 프로세서)
SM320C6201-EP 향상된 제품 C6201 고정 소수점 DSP SM320C6455-EP EP(Enhanced Product) C6455 고정 소수점 DSP SMJ320C6201B 고정 소수점 디지털 신호 프로세서, 군사용 SMJ320C6203 군사용 등급 C62x 고정 소수점 DSP - 세라믹 패키지 TMS320C6202B C62x 고정 소수점 DSP - 최대 300MHz, 384KB TMS320C6203B C62x 고정 소수점 DSP - 최대 300MHz, 896KB TMS320C6204 고정소수점 디지털 신호 프로세서 TMS320C6205 고정소수점 디지털 신호 프로세서 TMS320C6211B C62x 고정 소수점 DSP - 최대 167MHz TMS320C6412 C64x 고정 소수점 DSP - 최대 720MHz, McBSP, McASP, I2cC, 이더넷 TMS320C6414 C64x 고정 소수점 DSP - 최대 720MHz, McBSP TMS320C6414T C64x 고정 소수점 DSP - 최대 1GHz, McBSP TMS320C6415 C64x 고정 소수점 DSP - 최대 720MHz, McBSP, PCI TMS320C6415T C64x 고정 소수점 DSP - 최대 850MHz, McBSP, PCI TMS320C6416 C64x 고정 소수점 DSP - 최대 720MHz, McBSP, PCI, VCP/TCP TMS320C6416T C64x 고정 소수점 DSP - 최대 850MHz, McBSP, PCI, VCP/TCP TMS320C6421 C64x+ 고정 소수점 DSP - 최대 600MHz, 8비트 EMIFA, 16비트 DDR2, SDRAM TMS320C6421Q C64x+ 고정 소수점 DSP - 최대 600MHz, 8비트 EMIFA, 16비트 DDR2 TMS320C6424 C64x+ 고정 소수점 DSP - 최대 600MHz, 16/8비트 EMIFA, 32/16비트 DDR2, SDRAM TMS320C6424Q C64x+ 고정 소수점 DSP - 최대 600MHz, 16/8비트 EMIFA, 32/16비트 DDR2 TMS320C6452 C64x+ 고정 소수점 DSP - 최대 900MHz, 1Gbps 이더넷 TMS320C6454 C64x+ 고정 소수점 DSP - 최대 1GHz, 64비트 EMIFA, 32/16비트 DDR2, 1Gbps 이더넷 TMS320C6455 C64x+ 고정 소수점 DSP 최대 1.2GHz, 64비트 EMIFA, 32/16비트 DDR2, 1Gbps 이더넷 TMS320C6457 통신 인프라 디지털 신호 프로세서 TMS320C6474 멀티코어 디지털 신호 프로세서 TMS320DM640 비디오/이미징 고정 소수점 디지털 신호 프로세서 TMS320DM641 비디오/이미징 고정 소수점 디지털 신호 프로세서 TMS320DM642 비디오/이미징 고정 소수점 디지털 신호 프로세서 TMS320DM642Q 비디오/이미징 고정 소수점 디지털 신호 프로세서 TMS320DM6431 디지털 미디어 프로세서 TMS320DM6431Q 디지털 미디어 프로세서, 최대 2400MIPS, 300MHz 클럭 속도 TMS320DM6433 디지털 미디어 프로세서 TMS320DM6435 디지털 미디어 프로세서 TMS320DM6435Q 디지털 미디어 프로세서, 최대 4800MIPS, 600MHz 클록 속도, McASP 1개, McBSP 1개 TMS320DM6437 디지털 미디어 프로세서 TMS320DM6437Q 디지털 미디어 프로세서, 최대 4800MIPS, 600MHz 클록 속도, MCASP 1개, McBSP 2개 TMS320DM6441 DaVinci 디지털 미디어 시스템 온 칩 TMS320DM6443 DaVinci 디지털 미디어 시스템 온 칩 TMS320DM6446 DaVinci 디지털 미디어 시스템 온 칩
드라이버 또는 라이브러리

TELECOMLIB — 텔레콤 및 미디어 라이브러리 - TMS320C64x+ 및 TMS320C55x 프로세서를 위한 FAXLIB, VoLIB 및 AEC/AER

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
소프트웨어 코덱

TMDXDAISXDM — eXpressDSP 알고리즘 표준 – xDAIS 개발자 키트 및 xDM

xDAIS and xDM

The eXpressDSP™ Algorithm Interoperability Standard (xDAIS) and the eXpressDSP Digital Media (xDM) standard fully leverage the ability of DSPs to perform a wide range of multimedia functions on a single device. eXpressDSP compliance is achieved by adhering to these standards. To (...)

사용 설명서: PDF
시뮬레이션 모델

DM6435 ZDU BSDL Model (Rev. A)

SPRM227A.ZIP (10 KB) - BSDL Model
시뮬레이션 모델

DM6435 ZDU IBIS Model (Rev. B)

SPRM233B.ZIP (267 KB) - IBIS Model
시뮬레이션 모델

DM6435 ZWT BSDL Model (Rev. A)

SPRM226A.ZIP (10 KB) - BSDL Model
시뮬레이션 모델

DM6435 ZWT IBIS Model (Rev. B)

SPRM232B.ZIP (267 KB) - IBIS Model
패키지 CAD 기호, 풋프린트 및 3D 모델
BGA (ZDU) 376 Ultra Librarian
NFBGA (ZWT) 361 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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