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DSP type 1 C64x DSP (max) (MHz) 513, 594, 810 CPU 32-/64-bit Operating system DSP/BIOS, Integrity, Linux, Neutrino, PrOS, Windows Embedded CE Ethernet MAC 10/100 Rating Catalog Operating temperature range (°C) -40 to 105
DSP type 1 C64x DSP (max) (MHz) 513, 594, 810 CPU 32-/64-bit Operating system DSP/BIOS, Integrity, Linux, Neutrino, PrOS, Windows Embedded CE Ethernet MAC 10/100 Rating Catalog Operating temperature range (°C) -40 to 105
NFBGA (ZWT) 361 256 mm² 16 x 16
  • High-Performance Digital Media SoC
    • 513-, 594-, 810-MHz C64x+™ Clock Rates
    • 256.5-, 297-, 405-MHz ARM926EJ-S™ Clock Rates
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 4104, 4752, 6480 C64x+ MIPS
    • Fully Software-Compatible With C64x / ARM9™
    • Extended Temperature Devices Available
  • Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
    • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 32K-Byte L1P Program RAM/Cache (Direct Mapped)
    • 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative)
    • 64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • ARM926EJ-S Core
    • Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
    • DSP Instruction Extensions and Single Cycle MAC
    • ARM® Jazelle®: Technology
    • EmbeddedICE-RT™ Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • 16K-Byte RAM
    • 8K-Byte ROM
  • Embedded Trace Buffer™ (ETB11™) With 4KB Memory for ARM9 Debug
  • Endianness: Little Endian for ARM and DSP
  • Video Imaging Co-Processor (VICP)
  • Video Processing Subsystem
    • Front End Provides:
      • CCD and CMOS Imager Interface
      • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
      • Preview Engine for Real-Time Image Processing
      • Glueless Interface to Common Video Decoders
      • Histogram Module
      • Auto-Exposure, Auto-White Balance and Auto-Focus Module
      • Resize Engine Resize
        • Images From 1/4x to 4x
        • Separate Horizontal/Vertical Control
    • Back End Provides:
      • Hardware On-Screen Display (OSD)
      • Four 54-MHz DACs for a Combination of
        • Composite NTSC/PAL Video
        • Luma/Chroma Separate Video (S-video)
        • Component (YPbPr or RGB) Video (Progressive)
      • Digital Output
        • 8-/16-bit YUV or up to 24-Bit RGB
        • HD Resolution
        • Up to 2 Video Windows
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
      • Up to 167-MHz Controller (A-513, -594)
      • Up to 189-MHz Controller (-810)
    • Asynchronous 16-Bit-Wide EMIF (EMIFA) With 128M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-/16-Bit-Wide Data)
        • NAND (8-/16-Bit-Wide Data)
  • Flash Card Interfaces
    • Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
    • Compact Flash Controller With True IDE Mode
    • SmartMedia
  • Enhanced Direct-Memory-Access (EDMA3) Controller (64 Independent Channels)
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watch Dog Timer
  • Three UARTs (One with RTS and CTS Flow Control)
  • One Serial Peripheral Interface (SPI) With Two Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Audio Serial Port (ASP)
    • I2S
    • AC97 Audio Codec Interface
    • Standard Voice Codec Interface (AIC12)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
  • VLYNQ™ Interface (FPGA Interface)
  • Host Port Interface (HPI) with 16-Bit Multiplexed Address/Data
  • USB Port With Integrated 2.0 PHY
    • USB 2.0 High-/Full-Speed (480-Mbps) Client
    • USB 2.0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device)
  • Three Pulse Width Modulator (PWM) Outputs
  • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash or UART
  • ATA/ATAPI I/F (ATA/ATAPI-6 Specification)
  • Individual Power-Saving Modes for ARM/DSP
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • Up to 71 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • 361-Pin Pb-Free BGA Package(ZWT Suffix), 0.8-mm Ball Pitch
  • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal (513, 594)
  • 3.3-V and 1.8-V I/O, 1.2-V DAC and USB, 1.3-V Internal (810 only)
  • Applications:
    • Digital Media
    • Networked Media Encode/Decode
    • Video Imaging

All other trademarks are the property of their respective owners

  • High-Performance Digital Media SoC
    • 513-, 594-, 810-MHz C64x+™ Clock Rates
    • 256.5-, 297-, 405-MHz ARM926EJ-S™ Clock Rates
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 4104, 4752, 6480 C64x+ MIPS
    • Fully Software-Compatible With C64x / ARM9™
    • Extended Temperature Devices Available
  • Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
    • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 32K-Byte L1P Program RAM/Cache (Direct Mapped)
    • 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative)
    • 64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • ARM926EJ-S Core
    • Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
    • DSP Instruction Extensions and Single Cycle MAC
    • ARM® Jazelle®: Technology
    • EmbeddedICE-RT™ Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • 16K-Byte RAM
    • 8K-Byte ROM
  • Embedded Trace Buffer™ (ETB11™) With 4KB Memory for ARM9 Debug
  • Endianness: Little Endian for ARM and DSP
  • Video Imaging Co-Processor (VICP)
  • Video Processing Subsystem
    • Front End Provides:
      • CCD and CMOS Imager Interface
      • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
      • Preview Engine for Real-Time Image Processing
      • Glueless Interface to Common Video Decoders
      • Histogram Module
      • Auto-Exposure, Auto-White Balance and Auto-Focus Module
      • Resize Engine Resize
        • Images From 1/4x to 4x
        • Separate Horizontal/Vertical Control
    • Back End Provides:
      • Hardware On-Screen Display (OSD)
      • Four 54-MHz DACs for a Combination of
        • Composite NTSC/PAL Video
        • Luma/Chroma Separate Video (S-video)
        • Component (YPbPr or RGB) Video (Progressive)
      • Digital Output
        • 8-/16-bit YUV or up to 24-Bit RGB
        • HD Resolution
        • Up to 2 Video Windows
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
      • Up to 167-MHz Controller (A-513, -594)
      • Up to 189-MHz Controller (-810)
    • Asynchronous 16-Bit-Wide EMIF (EMIFA) With 128M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-/16-Bit-Wide Data)
        • NAND (8-/16-Bit-Wide Data)
  • Flash Card Interfaces
    • Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
    • Compact Flash Controller With True IDE Mode
    • SmartMedia
  • Enhanced Direct-Memory-Access (EDMA3) Controller (64 Independent Channels)
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watch Dog Timer
  • Three UARTs (One with RTS and CTS Flow Control)
  • One Serial Peripheral Interface (SPI) With Two Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Audio Serial Port (ASP)
    • I2S
    • AC97 Audio Codec Interface
    • Standard Voice Codec Interface (AIC12)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
  • VLYNQ™ Interface (FPGA Interface)
  • Host Port Interface (HPI) with 16-Bit Multiplexed Address/Data
  • USB Port With Integrated 2.0 PHY
    • USB 2.0 High-/Full-Speed (480-Mbps) Client
    • USB 2.0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device)
  • Three Pulse Width Modulator (PWM) Outputs
  • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash or UART
  • ATA/ATAPI I/F (ATA/ATAPI-6 Specification)
  • Individual Power-Saving Modes for ARM/DSP
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • Up to 71 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • 361-Pin Pb-Free BGA Package(ZWT Suffix), 0.8-mm Ball Pitch
  • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal (513, 594)
  • 3.3-V and 1.8-V I/O, 1.2-V DAC and USB, 1.3-V Internal (810 only)
  • Applications:
    • Digital Media
    • Networked Media Encode/Decode
    • Video Imaging

All other trademarks are the property of their respective owners

The TMS320DM6446 (also referenced as DM6446) leverages TI's DaVinci™ technology to meet the networked media encode and decode application processing needs of next-generation embedded devices.

The DM6446 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the DM6446 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+™ DSP core and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core incorporates: A coprocessor 15 (CP15) and protection module Data and program Memory Management Units (MMUs) with table look-aside buffers. Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of the C64x+™ DSP with added functionality and an expanded instruction set.

Any reference to the C64x™ DSP or C64x™ CPU also applies, unless otherwise noted, to the C64x+™ DSP and C64x+™ CPU, respectively.

With performance of up to 6480 million instructions per second (MIPS) at a clock rate of 810 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units--two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 3240 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 6480 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The DM6446 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6446 core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: 2 configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; one audio serial port (ASP); 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; up to 71-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; and 2 external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The DM6446 device includes a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals: 1 Video Processing Front-End (VPFE) input used for video capture, 1 Video Processing Back-End (VPBE) output with imaging co-processor (VICP) used for display.

The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine (Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or CCD and converts from an RGB Bayer Pattern to YUV4:2:2. The Histogram and H3A modules provide statistical information on the raw color data for use by the DM6446. The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.

The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM644x and the network. The DM6446 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the ARM, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the ARM, allowing the ARM to poll the link status of the device without continuously performing costly MDIO accesses.

The HPI, I2C, SPI, USB2.0, and VLYNQ ports allow DM6446 to easily control peripheral devices and/or communicate with host processors. The DM6446 also provides multimedia card support, MMC/SD, with SDIO support.

The DM6446 also includes a Video/Imaging Co-processor (VICP) to offload many video and imaging processing tasks from the DSP core, making more DSP MIPS available for common video and imaging algorithms. For more information on the VICP enhanced codecs, such as H.264 and MPEG4, please contact your nearest TI sales representative.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides listed in Section 2.8.3.1, Related Documentation From Texas Instruments.

The DM6446 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

The TMS320DM6446 (also referenced as DM6446) leverages TI's DaVinci™ technology to meet the networked media encode and decode application processing needs of next-generation embedded devices.

The DM6446 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the DM6446 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+™ DSP core and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core incorporates: A coprocessor 15 (CP15) and protection module Data and program Memory Management Units (MMUs) with table look-aside buffers. Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of the C64x+™ DSP with added functionality and an expanded instruction set.

Any reference to the C64x™ DSP or C64x™ CPU also applies, unless otherwise noted, to the C64x+™ DSP and C64x+™ CPU, respectively.

With performance of up to 6480 million instructions per second (MIPS) at a clock rate of 810 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units--two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 3240 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 6480 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The DM6446 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6446 core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: 2 configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; one audio serial port (ASP); 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; up to 71-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; and 2 external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The DM6446 device includes a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals: 1 Video Processing Front-End (VPFE) input used for video capture, 1 Video Processing Back-End (VPBE) output with imaging co-processor (VICP) used for display.

The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine (Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or CCD and converts from an RGB Bayer Pattern to YUV4:2:2. The Histogram and H3A modules provide statistical information on the raw color data for use by the DM6446. The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.

The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM644x and the network. The DM6446 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the ARM, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the ARM, allowing the ARM to poll the link status of the device without continuously performing costly MDIO accesses.

The HPI, I2C, SPI, USB2.0, and VLYNQ ports allow DM6446 to easily control peripheral devices and/or communicate with host processors. The DM6446 also provides multimedia card support, MMC/SD, with SDIO support.

The DM6446 also includes a Video/Imaging Co-processor (VICP) to offload many video and imaging processing tasks from the DSP core, making more DSP MIPS available for common video and imaging algorithms. For more information on the VICP enhanced codecs, such as H.264 and MPEG4, please contact your nearest TI sales representative.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides listed in Section 2.8.3.1, Related Documentation From Texas Instruments.

The DM6446 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

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유형 직함 날짜
* Data sheet TMS320DM6446 Digital Media System-on-Chip datasheet (Rev. H) 2010/09/30
* Errata TMS320DM6446 Digital Media SoC Silicon Errata (Revs 2.3, 2.1, 1.3, 1.2 & 1.1) (Rev. N) 2010/07/23
Application note High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 2023/02/24
User guide TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W) 2012/08/21
User guide TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U) 2012/08/21
User guide Emulation and Trace Headers Technical Reference Manual (Rev. I) 2012/08/09
Application note Introduction to TMS320C6000 DSP Optimization 2011/10/06
User guide TMS320DM644x DMSoC 64-bit Timer User's Guide 2011/08/01
User guide TMS320C6000 Programmer's Guide (Rev. K) 2011/07/11
User guide TMS320DM644x DMSoC Inter-Integrated Circuit (I2C) Peripheral User's Guide (Rev. F) 2011/03/25
User guide TMS320DM644x DMSoC Video Processing Back End (VPBE) User's Guide (Rev. D) 2011/01/27
User guide TMS320DM644x DMSoC DDR2 Memory Controller User's Guide (Rev. E) 2011/01/12
User guide TMS320DM644x DMSoC EMAC/MDIO Module User's Guide (Rev. B) 2010/12/23
User guide TMS320DM644x DMSoC Video Processing Front End (VPFE) User's Guide (Rev. H) 2010/08/25
User guide TMS320DM644x DMSoC General-Purpose Input/Output (GPIO) User's Guide (Rev. A) 2010/08/19
Application note TMS320DM6446/3 Power Consumption Summary (Rev. B) 2010/08/16
User guide TMS320DM644x DMSoC Pulse-Width Modulator (PWM) User's Guide (Rev. A) 2010/08/06
User guide TMS320C64x+ DSP Megamodule Reference Guide (Rev. K) 2010/08/03
User guide TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) 2010/07/30
User guide TMS320DM644x DMSoC ARM Subsystem Reference Guide (Rev. C) 2010/07/21
Application note Migrating From TMS320DM6446 594 MHz to 810 MHz 2010/07/20
Application note Migrating From TMS320DM644x v.2.1 ROM Bootloader to 2.3 Version 2010/07/20
User guide TMS320DM644x DMSoC Universal Serial Bus (USB) Controller User's Guide (Rev. G) 2010/06/02
User guide TMS320C6000 Assembly Language Tools v 7.0 User's Guide (Rev. S) 2010/03/18
User guide TMS320C6000 Optimizing Compiler v 7.0 User's Guide (Rev. Q) 2010/03/18
Application note USB Compliance Checklist (Rev. A) 2010/03/10
Application note Running a TMS320C64x+ Codec Across TMS320C64x+ Based DSP Platforms 2009/09/24
Application note Booting and Flashing via the DaVinci TMS320DM644x Serial Interface (Rev. A) 2009/09/10
Application note LSP 2.10 DaVinci Linux Drivers (Rev. A) 2009/07/08
Application note Common Object File Format (COFF) 2009/04/15
Application note Ultrasound Scan Conversion on TI's C64x+ DSPs 2009/04/03
User guide TMS320DM644x DMSoC Asynchronous External Memory Interface (EMIF) User's Guide (Rev. C) 2009/02/24
User guide TMS320DM644x DMSoC Host Port Interface (HPI) User's Guide (Rev. B) 2009/02/22
User guide TMS320C64x+ DSP Cache User's Guide (Rev. B) 2009/02/11
Application note De-Interlacing and YUV 4:2:2 to 4:2:0 Conversion on DM6446 Using the Resizer (Rev. B) 2008/12/17
Application note Booting DaVinci EVM from NAND Flash (Rev. A) 2008/12/15
Application note 5 VIN solution using DCDC Controllers, a LDO, and a Digitally Prog. Sequencer 2008/11/24
Application note Migrating from TMS320DM6446 to TMS320DM6467 2008/11/17
White paper See the difference:DSPs in medical imaging 2008/10/31
More literature DaVinci Technology Overview Brochure (Rev. B) 2008/09/27
Application note Migrating from EDMA v2.0 to EDMA v3.0 TMS320C64X DSP (Rev. A) 2008/08/21
Application note Understanding the Davinci Preview Engine (Rev. A) 2008/07/23
Application note Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A) 2008/07/17
Application note Understanding the Davinci Resizer (Rev. B) 2008/07/17
Application note Implementing the DDR2 PCB Layout on the TMS320DM644x DMSoC (Rev. G) 2008/06/16
Application note Building a Small Embedded Linux Kernel Example (Rev. A) 2008/05/27
User guide TMS320DM644x DMSoC Multimedia Card (MMC)/Secure Digital (SD) Card Controller UG (Rev. D) 2008/05/27
User guide TMS320C6000 Assembly Language Tools v 6.1 User's Guide (Rev. Q) 2008/05/15
User guide TMS320C6000 Optimizing Compiler v 6.1 User's Guide (Rev. O) 2008/05/15
User guide TMS320C64x+ DSP Image/Video Processing Library (v2.0) Programmer's Reference (Rev. A) 2008/05/05
Application note TMS320DM644x Thermal Considerations (Rev. A) 2008/04/23
Application note TMS320DM6441 Power Consumption Summary Application Report 2008/04/08
User guide TMS320DM644x DMSoC Universal Asynchronous Receiver/Transmitter (UART) UG (Rev. A) 2008/04/08
User guide TMS320C64x+ DSP Little-Endian Library Programmer's Reference (Rev. B) 2008/03/06
Application note Creating a TMS320DM6446 Audio Encode Example Using XDC Tools (Rev. A) 2008/02/26
User guide TMS320DM644x DMSoC Enhanced Direct Memory Access (EDMA) Controller User's Guide (Rev. D) 2008/02/25
Application note Building GStreamer 2008/01/11
Application note Migrating from TMS320DM6446 to TMS320DM6437 2007/11/05
Application note Changing the DVEVM Memory Map 2007/09/26
User guide TMS320DM644x DMSoC VLYNQ Port User's Guide (Rev. A) 2007/09/20
User guide TMS320DM644x DMSoC Audio Serial Port (ASP) User's Guide (Rev. B) 2007/09/17
Application note Motion JPEG Demo on TMS320DM6446 (Rev. A) 2007/09/11
Application note Running Demo via ddd on the DVEVM 2007/07/30
Application note Using Static IP Between Linux Host and the DVEVM 2007/07/30
Application note Compact Flash (CF) Support on the DVEVM 2007/07/25
Application note Host USB Support on the DVEVM 2007/07/20
Application note Decode Demo for the DaVinci DVEVM/DVSDK 1.2 (Rev. A) 2007/06/27
Application note Digital Video Using DaVinci SoC 2007/06/27
Application note Encode Demo for the DaVinci DVEVM/DVSDK 1.2 (Rev. A) 2007/06/27
Application note EncodeDecode Demo for the DaVinci DVEVM/DVSDK 1.2 (Rev. A) 2007/06/27
Application note Measuring Video Quality With the TMS320DM6446 DVSDK 2007/05/08
User guide TMS320DM644x DMSoC Peripherals Overview Reference Guide (Rev. C) 2007/04/18
Product overview TMS320C6000 DSP TCP/IP Stack Software (Rev. C) 2007/04/04
EVM User's guide TMS320DM644x DVEVM Windows CE v5.0 BSP Codec Engine User’s Guide 2007/03/23
EVM User's guide TMS320DM644x DVEVM Windows CE v5.0 Codec Engine Binary User's Guide 2007/03/23
Product overview DaVinci Technology - Digital Video Innovation Product Bulletin (Rev. D) 2007/02/13
More literature Overview of DaVinci™ TMS320DM644x Digital Media Portfolio (Rev. B) 2007/02/13
User guide TMS320DM644x DMSoC Serial Peripheral Interface (SPI) User's Guide (Rev. A) 2007/02/07
Application note DaVinci Technology Background and Specifications (Rev. A) 2007/01/04
Application note Basic Application Loading over the Serial Interface for the DaVinci TMS320DM644x 2006/12/21
Product overview Portable Media Player Based on DaVinci Technology 2006/11/14
Product overview Universal IP Player Solution from ATEME 2006/11/02
Application note DaVinci System Level Benchmarking Measurements 2006/09/28
Product overview DaVinci Benchmarks Product Bulletin (Rev. A) 2006/09/12
Application note Fast Development with DaVinci On Screen Display (OSD) 2006/07/06
User guide TMS320C64x+ DSP Big-Endian Library Programmer's Reference 2006/03/10
User guide TMS320C64x+ Image/Video Processing Library Programmer's Reference 2006/03/10
Application note Migrating from EDMA v2.0 to EDMA v3.0 for TMS320DM644X DMSoC 2005/12/03
User guide TMS320DM644x DMSoC ATA Controller User's Guide 2005/12/03
User guide TMS320DM644x DMSoC DSP Subsystem Reference Guide 2005/12/03
Application note Migrating from TMS320C64x to TMS320C64x+ (Rev. A) 2005/10/20

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

디버그 프로브

TMDSADP — 적응형 클로킹 JTAG 에뮬레이터 어댑터

TMDSADP1420 adapter – used for connecting TI and 3rd party XDS510 and XDS560-class emulators with a 14 pin native connector to the TMDXEVM6446 or customer boards with a compact (CTI) 20-pin header. The adapter improves signal integrity, translates voltages, and can optionally provide adaptive (...)

사용 설명서: PDF
디버그 프로브

TMDSEMU200-U — XDS200 USB 디버그 프로브

XDS200은 TI 임베디드 디바이스 디버깅에 사용되는 디버그 프로브(에뮬레이터)입니다. XDS200은 저렴한 XDS110 및 고성능 XDS560v2에 비해 저렴한 비용으로 우수한 성능을 균형 있게 제공합니다. 단일 포드에서 광범위한 표준(IEEE1149.1, IEEE1149.7, SWD)을 지원합니다. 모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 Arm® 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 코어 추적의 경우 XDS560v2 PRO TRACE가 (...)

TI.com에서 구매 불가
디버그 프로브

TMDSEMU560V2STM-U — XDS560v2 시스템 추적 USB 디버그 프로브

XDS560v2는 디버그 프로브의 XDS560™ 제품군 중 최고의 성능을 가진 제품으로, 기존의 JTAG 표준(IEEE1149.1)과 cJTAG(IEEE1149.7)를 모두 지원합니다. SWD(직렬 와이어 디버그)는 지원하지 않습니다.

모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 ARM 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 추적의 경우 XDS560v2 PRO TRACE가 필요합니다.

XDS560v2는 MIPI HSPT 60핀 커넥터(TI 14핀, (...)

TI.com에서 구매 불가
디버그 프로브

TMDSEMU560V2STM-UE — XDS560v2 시스템 추적 USB 및 이더넷 디버그 프로브

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

TI.com에서 구매 불가
소프트웨어 개발 키트(SDK)

LINUXDVSDK-DV — Linux DVSDK(디지털 비디오 소프트웨어 개발 키트) v2x/v3x - DaVinci 디지털 미디어 프로세서

Effective Oct 2010 - Linux DVSDK v4 has been released. For DaVinci™ devices not listed above, search TI.com for your device part number; This product page will have a link to your current DVSDK.

The Linux™ Digital Video Software Development Kits (DVSDKs) enable DaVinci system integrators to (...)

애플리케이션 소프트웨어 및 프레임워크

TMDMFP — 멀티미디어 프레임워크 제품(MFP) - 코덱 엔진, 프레임워크 구성 요소 및 XDAIS

Multimedia Framework Products (MFP)

A major advantage of programmable signal processors over fixed-function devices is their ability to accelerate multiple multimedia functions and provide flexible environments to enable user customization. However, sharing scarce embedded hardware resources between (...)

사용 설명서: PDF
드라이버 또는 라이브러리

SPRC122 C62x/C64x Fast Run-Time Support Library

The C62x/64x FastRTS Library is an optimized, floating-point function library for C programmers using either TMS320C62x or TMS320C64x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By replacing the current (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
DSP(디지털 신호 프로세서)
SM320C6201-EP 향상된 제품 C6201 고정 소수점 DSP SM320C6455-EP EP(Enhanced Product) C6455 고정 소수점 DSP SMJ320C6201B 고정 소수점 디지털 신호 프로세서, 군사용 SMJ320C6203 군사용 등급 C62x 고정 소수점 DSP - 세라믹 패키지 TMS320C6202B C62x 고정 소수점 DSP - 최대 300MHz, 384KB TMS320C6203B C62x 고정 소수점 DSP - 최대 300MHz, 896KB TMS320C6204 고정소수점 디지털 신호 프로세서 TMS320C6205 고정소수점 디지털 신호 프로세서 TMS320C6211B C62x 고정 소수점 DSP - 최대 167MHz TMS320C6412 C64x 고정 소수점 DSP - 최대 720MHz, McBSP, McASP, I2cC, 이더넷 TMS320C6414 C64x 고정 소수점 DSP - 최대 720MHz, McBSP TMS320C6414T C64x 고정 소수점 DSP - 최대 1GHz, McBSP TMS320C6415 C64x 고정 소수점 DSP - 최대 720MHz, McBSP, PCI TMS320C6415T C64x 고정 소수점 DSP - 최대 850MHz, McBSP, PCI TMS320C6416 C64x 고정 소수점 DSP - 최대 720MHz, McBSP, PCI, VCP/TCP TMS320C6416T C64x 고정 소수점 DSP - 최대 850MHz, McBSP, PCI, VCP/TCP TMS320C6421 C64x+ 고정 소수점 DSP - 최대 600MHz, 8비트 EMIFA, 16비트 DDR2, SDRAM TMS320C6421Q C64x+ 고정 소수점 DSP - 최대 600MHz, 8비트 EMIFA, 16비트 DDR2 TMS320C6424 C64x+ 고정 소수점 DSP - 최대 600MHz, 16/8비트 EMIFA, 32/16비트 DDR2, SDRAM TMS320C6424Q C64x+ 고정 소수점 DSP - 최대 600MHz, 16/8비트 EMIFA, 32/16비트 DDR2 TMS320C6452 C64x+ 고정 소수점 DSP - 최대 900MHz, 1Gbps 이더넷 TMS320C6454 C64x+ 고정 소수점 DSP - 최대 1GHz, 64비트 EMIFA, 32/16비트 DDR2, 1Gbps 이더넷 TMS320C6455 C64x+ 고정 소수점 DSP 최대 1.2GHz, 64비트 EMIFA, 32/16비트 DDR2, 1Gbps 이더넷 TMS320C6457 통신 인프라 디지털 신호 프로세서 TMS320C6474 멀티코어 디지털 신호 프로세서 TMS320DM640 비디오/이미징 고정 소수점 디지털 신호 프로세서 TMS320DM641 비디오/이미징 고정 소수점 디지털 신호 프로세서 TMS320DM642 비디오/이미징 고정 소수점 디지털 신호 프로세서 TMS320DM642Q 비디오/이미징 고정 소수점 디지털 신호 프로세서 TMS320DM6431 디지털 미디어 프로세서 TMS320DM6431Q 디지털 미디어 프로세서, 최대 2400MIPS, 300MHz 클럭 속도 TMS320DM6433 디지털 미디어 프로세서 TMS320DM6435 디지털 미디어 프로세서 TMS320DM6435Q 디지털 미디어 프로세서, 최대 4800MIPS, 600MHz 클록 속도, McASP 1개, McBSP 1개 TMS320DM6437 디지털 미디어 프로세서 TMS320DM6437Q 디지털 미디어 프로세서, 최대 4800MIPS, 600MHz 클록 속도, MCASP 1개, McBSP 2개 TMS320DM6441 DaVinci 디지털 미디어 시스템 온 칩 TMS320DM6443 DaVinci 디지털 미디어 시스템 온 칩 TMS320DM6446 DaVinci 디지털 미디어 시스템 온 칩
드라이버 또는 라이브러리

SPRC831 — VICP(Video Imaging Co-Processor) 신호 처리 라이브러리

Texas Instruments VICP Signal processing library is a collection of highly tuned SW algorithms that execute on the VICP H/W accelerator. The library allows the application developer to effectively utilize the VICP performance without spending significant time in developing software for the (...)
사용 설명서: PDF
드라이버 또는 라이브러리

TELECOMLIB — 텔레콤 및 미디어 라이브러리 - TMS320C64x+ 및 TMS320C55x 프로세서를 위한 FAXLIB, VoLIB 및 AEC/AER

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
소프트웨어 코덱

C64XPLUSCODECS — 코덱 - 비디오 및 음성 - C64x+ 기반 디바이스(OMAP35x, C645x, C647x, DM646, DM644x, DM643x)

TI 코덱은 무료이고 프로덕션 라이선스와 함께 제공되며 지금 다운로드할 수 있습니다. 모두 프로덕션급 테스트를 통해 비디오 및 음성 애플리케이션에 원활하게 통합되는 것으로 확인되었습니다. 소프트웨어 다운로드 버튼(위)을 클릭하면 테스트를 거친 최신 버전의 코덱에 액세스할 수 있습니다. 데이터시트와 릴리스 노트는 해당 페이지와 각 설치 프로그램에 있습니다.

 

 

추가 정보:

소프트웨어 코덱

DM644XCODECS Codecs for DM644x - Software and Documentation

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio, video and voice applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)

지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

제품
DSP(디지털 신호 프로세서)
SM320DM6446-HIREL 높은 안정성 제품 디지털 미디어 DM6446 프로세서 TMS320DM6441 DaVinci 디지털 미디어 시스템 온 칩 TMS320DM6443 DaVinci 디지털 미디어 시스템 온 칩 TMS320DM6446 DaVinci 디지털 미디어 시스템 온 칩
다운로드 옵션
소프트웨어 코덱

TMDXDAISXDM — eXpressDSP 알고리즘 표준 – xDAIS 개발자 키트 및 xDM

xDAIS and xDM

The eXpressDSP™ Algorithm Interoperability Standard (xDAIS) and the eXpressDSP Digital Media (xDM) standard fully leverage the ability of DSPs to perform a wide range of multimedia functions on a single device. eXpressDSP compliance is achieved by adhering to these standards. To (...)

사용 설명서: PDF
시뮬레이션 모델

DM6446 ZWT BSDL Model

SPRM203.ZIP (10 KB) - BSDL Model
시뮬레이션 모델

DM6446 ZWT BSDL version 2.1 Model (Rev. A)

SPRM325A.ZIP (8 KB) - BSDL Model
시뮬레이션 모델

DM6446 ZWT IBIS Model (Rev. C)

SPRM202C.ZIP (112 KB) - IBIS Model
시뮬레이션 모델

DM6446_DDR2 ZWT IBIS Model

SPRM450.ZIP (50 KB) - IBIS Model
패키지 CAD 기호, 풋프린트 및 3D 모델
NFBGA (ZWT) 361 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

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