전원 관리 LED 드라이버 차량용 LED 드라이버

TPIC6A595

활성

350mA/ch을 지원하는 8비트 시프트 레지스터

제품 상세 정보

Number of channels 8 Topology Open drain Rating Automotive Operating temperature range (°C) -40 to 125 Vin (min) (V) 4.5 Vin (max) (V) 5.5 Vout (max) (V) 50 Features Enable/Shutdown, Thermal shutdown
Number of channels 8 Topology Open drain Rating Automotive Operating temperature range (°C) -40 to 125 Vin (min) (V) 4.5 Vin (max) (V) 5.5 Vout (max) (V) 50 Features Enable/Shutdown, Thermal shutdown
PDIP (NE) 20 224.0214 mm² 24.51 x 9.14 SOIC (DW) 24 159.65 mm² 15.5 x 10.3
  • Low rDS(on) . . . 1 Typ
  • Output Short-Circuit Protection
  • Avalanche Energy . . . 75 mJ
  • Eight 350-mA DMOS Outputs
  • 50-V Switching Capability
  • Devices Are Cascadable
  • Low Power Consumption

  • Low rDS(on) . . . 1 Typ
  • Output Short-Circuit Protection
  • Avalanche Energy . . . 75 mJ
  • Eight 350-mA DMOS Outputs
  • 50-V Switching Capability
  • Devices Are Cascadable
  • Low Power Consumption

The TPIC6A595 is a monolithic, high-voltage, high-current power logic 8-bit shift register designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other medium-current or high-voltage loads. Each open-drain DMOS transistor features an independent chopping current-limiting circuit to prevent damage in the case of a short circuit.

This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit, D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when shiftregister clear (SRCLR)\ is high. When SRCLR\ is low, the input shift register is cleared. When output enable (G)\ is held high, all data in the output buffers is held low and all drain outputs are off. When G\ is held low, data from the storage register is transparent to the output buffers. The serial output (SER OUT) allows for cascading of the data from the shift register to additional devices.

Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and a 350-mA continuous sink current capability. When data in the output buffers is low, the DMOS-transistor outputs are off. When data is high, the DMOS-transistor outputs have sink current capability.

Separate power ground (PGND) and logic ground (LGND) terminals are provided to facilitate maximum system flexibility. All PGND terminals are internally connected, and each PGND terminal must be externally connected to the power system ground in order to minimize parasitic impedance. A single-point connection between LGND and PGND must be made externally in a manner that reduces crosstalk between the logic and load circuits.

The TPIC6A595 is offered in a thermally-enhanced dual-in-line (NE) package and a wide-body surface-mount (DW) package. The TPIC6A595 is characterized for operation over the operating case temperature range of -40°C to 125°C.

The TPIC6A595 is a monolithic, high-voltage, high-current power logic 8-bit shift register designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other medium-current or high-voltage loads. Each open-drain DMOS transistor features an independent chopping current-limiting circuit to prevent damage in the case of a short circuit.

This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit, D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when shiftregister clear (SRCLR)\ is high. When SRCLR\ is low, the input shift register is cleared. When output enable (G)\ is held high, all data in the output buffers is held low and all drain outputs are off. When G\ is held low, data from the storage register is transparent to the output buffers. The serial output (SER OUT) allows for cascading of the data from the shift register to additional devices.

Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and a 350-mA continuous sink current capability. When data in the output buffers is low, the DMOS-transistor outputs are off. When data is high, the DMOS-transistor outputs have sink current capability.

Separate power ground (PGND) and logic ground (LGND) terminals are provided to facilitate maximum system flexibility. All PGND terminals are internally connected, and each PGND terminal must be externally connected to the power system ground in order to minimize parasitic impedance. A single-point connection between LGND and PGND must be made externally in a manner that reduces crosstalk between the logic and load circuits.

The TPIC6A595 is offered in a thermally-enhanced dual-in-line (NE) package and a wide-body surface-mount (DW) package. The TPIC6A595 is characterized for operation over the operating case temperature range of -40°C to 125°C.

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관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀
TLC6A598 활성 항공 애플리케이션용 고전력 8비트 위상 변이 고신뢰성 드라이버 Pin-for-pin alternative with extended temperature range, wider input voltage range and additional protection features.

기술 자료

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유형 직함 날짜
* Data sheet Power Logic 8-Bit Shift Register datasheet (Rev. B) 2005/05/18

설계 및 개발

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시뮬레이션 툴

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PDIP (NE) 20 Ultra Librarian
SOIC (DW) 24 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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