TPS51200-Q1

활성

차량용 카탈로그 싱크/소스 DDR 터미네이션 레귤레이터

이 제품의 최신 버전이 있습니다

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TPS51200A-Q1 활성 싱크 및 소스 DDR 터미네이션 레귤레이터 This product has added features for increased robustness.

제품 상세 정보

Vin (min) (V) 1.1 Vin (max) (V) 3.5 Vout (max) (V) 1.8 Features S3/S5 Support Rating Automotive Operating temperature range (°C) -40 to 125 Iq (typ) (mA) 0.5 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3
Vin (min) (V) 1.1 Vin (max) (V) 3.5 Vout (max) (V) 1.8 Features S3/S5 Support Rating Automotive Operating temperature range (°C) -40 to 125 Iq (typ) (mA) 0.5 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3
VSON (DRC) 10 9 mm² 3 x 3
  • Qualified for Automotive Applications
  • AEC-Q100 Test Guidance With the Following Results:
    • Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C4B
  • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail
  • VLDOIN Voltage Range: 1.1 V to 3.5 V
  • Sink/Source Termination Regulator Includes Droop Compensation
  • Requires Minimum Output Capacitance of 20-µF (typically 3 × 10-µF MLCCs) for Memory Termination Applications (DDR)
  • PGOOD to Monitor Output Regulation
  • EN Input
  • REFIN Input Allows for Flexible Input Tracking Either Directly or Through Resistor Divider
  • Remote Sensing (VOSNS)
  • ±10-mA Buffered Reference (REFOUT)
  • Built-in Soft Start, UVLO and OCL
  • Thermal Shutdown
  • Meets DDR, DDR2 JEDEC Specifications; Supports DDR3, DDR3L, Low-Power DDR3 and DDR4 VTT Applications
  • VSON-10 Package With Exposed Thermal Pad
  • Qualified for Automotive Applications
  • AEC-Q100 Test Guidance With the Following Results:
    • Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C4B
  • Input Voltage: Supports 2.5-V Rail and 3.3-V Rail
  • VLDOIN Voltage Range: 1.1 V to 3.5 V
  • Sink/Source Termination Regulator Includes Droop Compensation
  • Requires Minimum Output Capacitance of 20-µF (typically 3 × 10-µF MLCCs) for Memory Termination Applications (DDR)
  • PGOOD to Monitor Output Regulation
  • EN Input
  • REFIN Input Allows for Flexible Input Tracking Either Directly or Through Resistor Divider
  • Remote Sensing (VOSNS)
  • ±10-mA Buffered Reference (REFOUT)
  • Built-in Soft Start, UVLO and OCL
  • Thermal Shutdown
  • Meets DDR, DDR2 JEDEC Specifications; Supports DDR3, DDR3L, Low-Power DDR3 and DDR4 VTT Applications
  • VSON-10 Package With Exposed Thermal Pad

The TPS51200-Q1 device is a sink and source double-data-rate (DDR) termination regulator specifically designed for low input voltage, low-cost, low-noise systems where space is a key consideration.

The TPS51200-Q1 device maintains a fast transient response and only requires a minimum output capacitance of 20 µF. The TPS51200-Q1 device supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, DDR3L, Low Power DDR3 and DDR4 VTT bus termination.

In addition, the TPS51200-Q1 device provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications.

The TPS51200-Q1 device is available in the thermally-efficient VSON-10 package, and is rated both green and Pb-free. The device is specified from –40°C to 125°C.

The TPS51200-Q1 device is a sink and source double-data-rate (DDR) termination regulator specifically designed for low input voltage, low-cost, low-noise systems where space is a key consideration.

The TPS51200-Q1 device maintains a fast transient response and only requires a minimum output capacitance of 20 µF. The TPS51200-Q1 device supports a remote sensing function and all power requirements for DDR, DDR2, DDR3, DDR3L, Low Power DDR3 and DDR4 VTT bus termination.

In addition, the TPS51200-Q1 device provides an open-drain PGOOD signal to monitor the output regulation and an EN signal that can be used to discharge VTT during S3 (suspend to RAM) for DDR applications.

The TPS51200-Q1 device is available in the thermally-efficient VSON-10 package, and is rated both green and Pb-free. The device is specified from –40°C to 125°C.

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기술 자료

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9개 모두 보기
유형 직함 날짜
* Data sheet TPS51200-Q1 Sink and Source DDR Termination Regulator datasheet (Rev. C) PDF | HTML 2016/07/25
Application note DDR VTT Power Solutions: A Competitive Analysis (Rev. A) 2020/07/09
Technical article Improving DDR Memory Performance in Automotive Applications PDF | HTML 2017/06/22
Application note Pwr Ref Design f/'C6472 12-Vin Digital Pwr Controllers and LDOs 2010/04/28
Application note Power Two Xilinx(TM) LX240 Virtex-6(TM) Devices 2010/04/20
Application note Power Ref Design for TMS320C6472 5Vin DC/DC Converters (1x C6472) 2010/03/31
Application note 'C6472 12Vin Flexible Pwr Design Using DCDC Controllers and LDOs (8x C6472) 2010/03/26
Application note Power Reference Design for the 'C6472, 12V DCDC Controllers, and LDOs 2010/03/26
Application note TMS320C6472 5V Input Pwr Design, Integrated FET DC/DC Converters and Controllers 2010/03/26

설계 및 개발

전원 공급 솔루션

TPS51200-Q1을 포함하는 솔루션을 살펴보세요. TI는 칩(SoC), 프로세서, 마이크로컨트롤러, 센서 또는 FPGA(Field Programmable Gate Array)의 TI와 비TI 시스템을 위한 전원 공급 솔루션을 제공합니다.

평가 보드

TPS51200EVM — TPS51200 싱크 소스 DDR 터미네이션 레귤레이터

TPS51200EVM 평가 보드인 HPA322A는 TI의 비용에 최적화된 DDR/DDR2/DDR3/LP DDR3 VTT 터미네이션 레귤레이터인 TPS51200의 성능과 특성을 평가하도록 설계되었습니다. TPS51200은 최소한의 외부 부품으로 DDR(2.5V/1.25V), DDR2(1.8V/0.9V), DDR3(1.5V/0.75V), LP DDR3(1.2V/0.6V) 사양을 지원하는 DDR 메모리에 적절한 터미네이션 전압 및 10mA 버퍼 레퍼런스 전압을 제공하도록 설계되었습니다.

사용 설명서: PDF
TI.com에서 구매 불가
시뮬레이션 모델

TPS51200 PSpice Average Model

SLVM069.ZIP (30 KB) - PSpice Model
시뮬레이션 모델

TPS51200 PSpice Transient Model (Rev. A)

SLVM068A.ZIP (38 KB) - PSpice Model
시뮬레이션 모델

TPS51200 TINA-TI Average Reference Design

SLUM150.TSC (755 KB) - TINA-TI Reference Design
시뮬레이션 모델

TPS51200 TINA-TI Average Spice Model

SLUM151.ZIP (17 KB) - TINA-TI Spice Model
시뮬레이션 모델

TPS51200 TINA-TI Start-Up Transient Reference Design

SLUM148.TSC (127 KB) - TINA-TI Reference Design
시뮬레이션 모델

TPS51200 TINA-TI Transient Spice Model

SLUM149.ZIP (18 KB) - TINA-TI Spice Model
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The TIDA-01425 is a subsystem reference design for automotive gateways focused on increasing bandwidth and processing power in gateway applications. The design implements Ethernet physical layer transceivers (PHYs) for increased bandwidth along with an automotive processor for greater processing (...)
Design guide: PDF
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This reference design provides an electronics subsystem designed to drive an automotive augmented reality (AR) head-up display (HUD). DLP® technology enables bright, crisp, highly saturated head-up displays that project critical driving information onto the windshield of the car, reducing (...)
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레퍼런스 디자인

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The TIDA-00346 design provides the power supply rails necessary for typical  entry-level application processors in automotive advanced driver assistance systems (ADAS) applications.  The design uses several individual DC/DC voltage regulators as well as load switches and linear regulators (...)
Test report: PDF
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패키지 CAD 기호, 풋프린트 및 3D 모델
VSON (DRC) 10 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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