UC1875-SP
- QML-V Qualified, SMD 5962-94555
- Rad-Tolerant: 50 kRad (Si) TID(1)
- Zero to 100% Duty Cycle Control
- Programmable Output Turn-On Delay
- Compatible with Voltage or Current Mode
Topologies - Practical Operation at Switching Frequencies to
1 MHz - Four 2-A Totem Pole Outputs
- 10-MHz Error Amplifier
- Undervoltage Lockout (UVLO)
- Low Startup Current – 150 µA
- Outputs Active Low During UVLO
- Soft-Start Control
- Latched Overcurrent Comparator With Full Cycle
Restart - Trimmed Reference
The UC1875-SP implements control of a bridge power stage by phase-shifting the switching of one half-bridge with respect to the other, allowing constant frequency pulse-width modulation in combination with resonant, zero-voltage switching for high efficiency performance at high frequencies. This circuit may be configured to provide control in either voltage or current mode operation, with a separate overcurrent shutdown for fast fault protection.
A programmable time delay is provided to insert a dead-time at the turn-on of each output stage. This delay, providing time to allow the resonant switching action, is independently controllable for each output pair (A-B, C-D).
With the oscillator capable of operation at frequencies in excess of 2 MHz, overall switching frequencies to 1 MHz are practical. In addition to the standard free running mode, with the CLOCKSYNC pin, the user may configure these devices to accept an external clock synchronization signal, or may lock together up to 5 units with the operational frequency determined by the fastest device.
Protective features include an undervoltage lockout which maintains all outputs in an active-low state until the supply reaches a 10.75-V threshold. 1.5 hysteresis is built in for reliable, boot-strapped chip supply. Overcurrent protection is provided, and will latch the outputs in the OFF state within 70 ns of a fault. The current-fault circuitry implements full-cycle restart operation.
Additional features include an error amplifier with bandwidth in excess of 7 MHz, a 5-V reference, provisions for soft-starting, and flexible ramp generation and slope compensation circuitry.
This device is available in hermetically sealed cerdip, surface mount, and ceramic leadless chip carrier packages for 55°C to 125°C operation.
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기술 자료
설계 및 개발
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패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
---|---|---|
CDIP (J) | 20 | Ultra Librarian |
CFP (W) | 24 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치