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微控制器 (MCU) 與處理器
微處理器和 DSP
汽車網路 SoC

DRA821U-Q1

現行

具有雙 Arm® Cortex® A72 、 4 埠乙太網路以及 4 通道 PCIe 的 SoC ，用於網路和運算

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DRA821U-Q1

現行
產品規格表 立即訂購

產品詳細資料

CPU 2 Arm Cortex-A72 Frequency (MHz) 2000 Coprocessors 4 Arm Cortex-R5F Protocols Ethernet, TSN PCIe 1 PCIe Gen 3 Features Networking Operating system FreeRTOS, INTEGRITY, Linux, QNX, SafeRTOS, VxWorks, u-velOSity Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection TI functional safety category Functional Safety-Compliant Rating Automotive Power supply solution LP8764-Q1, TPS6594-Q1 Operating temperature range (°C) -40 to 125 Edge AI enabled No
CPU 2 Arm Cortex-A72 Frequency (MHz) 2000 Coprocessors 4 Arm Cortex-R5F Protocols Ethernet, TSN PCIe 1 PCIe Gen 3 Features Networking Operating system FreeRTOS, INTEGRITY, Linux, QNX, SafeRTOS, VxWorks, u-velOSity Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection TI functional safety category Functional Safety-Compliant Rating Automotive Power supply solution LP8764-Q1, TPS6594-Q1 Operating temperature range (°C) -40 to 125 Edge AI enabled No
FCBGA (ALM) 433 295.84 mm² 17.2 x 17.2

Processor cores:

  • Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS
    • 1MB L2 shared cache per dual-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per A72 core
  • 4× Arm Cortex-R5F MCUs at up to 1.0 GHz with optional lockstep operation, 8K DMIPS
    • 32K I-Cache, 32K D-Cache, 64K L2 TCM
    • 2× Arm Cortex-R5F MCUs in isolated MCU subsystem
    • 2× Arm Cortex-R5F MCUs in general compute partition

    Memory subsystem:

  • 1MB of On-Chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types that comply with the JESD209-4B specification. (No support for byte mode LPDDR4 memories, or memories with more than 17 row address bits)
    • Supports speeds up to 3200 MT/s
    • 32-bit and 16-bit data bus with inline ECC bus up to 12.8GB/s
  • General-Purpose Memory Controller (GPMC)
  • 512KB on-chip SRAM in MAIN domain, protected by ECC

    Virtualization:

  • Hypervisor support in Arm Cortex-A72
  • Independent processing subsystems with Arm Cortex-A72, Arm Cortex-R5F with isolated safety MCU island
  • IO virtualization support
    • Peripheral Virtualization Unit (PVU) for low latency high bandwidth peripheral traffic
  • Multi-region firewall support for memory and peripheral isolation
  • Virtualization support with Ethernet, PCIe, and DMA

  • Device security (on select part numbers):

  • Secure boot with secure runtime support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 and IEC 61508 functional safety system design up to ASIL-D/SIL-3 targeted
    • Systematic capability up to ASIL-D/SIL-3 targeted
    • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
    • Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain
    • Hardware integrity up to ASIL-B/SIL-2 targeted for remainder of the Main Domain
    • FFI isolation provided between EMCU and the remainder of the Main Domain
    • Safety-related certification
      • ISO 26262 and IEC 61508 planned
  • AEC-Q100 qualified on part number variants ending in Q1

  • High-speed interfaces:

    • Integrated Ethernet TSN/AVB switch supporting up to 4 (DRA821U4) or 2 (DRA821U2) external ports:
      • One port supports 5Gb, 10Gb USXGMII/XFI
      • All ports support 2.5Gb SGMII
      • All ports support 1Gb SGMII/RGMII
      • DRA821U4: Any single port can support QSGMII (using all 4 internal ports)
      • Non-blocking wire-rate store and forward switch
      • InterVLAN (Layer3) routing support
      • Time synchronization support with IEEE 1588(annex D,E,F)
      • TSN/AVB support for traffic scheduling, shaping
      • Port mirroring feature for debug and diagnostics
      • Policing and rate limiting support
    • One RGMII/RMII port in safety MCU island
  • One PCI-Express Gen3 controller
    • Gen1, Gen2, and Gen3 operation with auto-negotiation
    • 4× lanes
  • One USB 3.1 Gen1 dual-role device subsystem
    • Supports type-C switching
    • Independently configurable as USB host, USB peripheral, or USB dual-role device

    Automotive interfaces:

  • Twenty CAN-FD ports
  • 12× Universal Asynchronous Receiver/Transmitter (UART)
  • 11× Serial Peripheral Interfaces (SPI)
  • One 8-channel ADC
  • 10× Inter-Integrated Circuit ( I2C™)
  • 2× Improved Inter-Integrated Circuit ( I3C)

    Audio interfaces:

  • 3× Multichannel Audio Serial Port (McASP) modules

    Flash memory interfaces:

  • Embedded Multi Media Card ( eMMC™ 5.1) interface
    • Support speeds of up to HS400
  • One Secure Digital 3.0/Secure Digital Input Output 3.0 (SD3.0/SDIO3.0) interfaces
  • One Octal SPI / Xccela™ / HyperBus™ Memory Controller (HBMC) interface
  • 16-nm FinFET technology
  • 17.2 mm x 17.2 mm, 0.8 mm pitch, IPC Class 3 PCB

Processor cores:

  • Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS
    • 1MB L2 shared cache per dual-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per A72 core
  • 4× Arm Cortex-R5F MCUs at up to 1.0 GHz with optional lockstep operation, 8K DMIPS
    • 32K I-Cache, 32K D-Cache, 64K L2 TCM
    • 2× Arm Cortex-R5F MCUs in isolated MCU subsystem
    • 2× Arm Cortex-R5F MCUs in general compute partition

    Memory subsystem:

  • 1MB of On-Chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types that comply with the JESD209-4B specification. (No support for byte mode LPDDR4 memories, or memories with more than 17 row address bits)
    • Supports speeds up to 3200 MT/s
    • 32-bit and 16-bit data bus with inline ECC bus up to 12.8GB/s
  • General-Purpose Memory Controller (GPMC)
  • 512KB on-chip SRAM in MAIN domain, protected by ECC

    Virtualization:

  • Hypervisor support in Arm Cortex-A72
  • Independent processing subsystems with Arm Cortex-A72, Arm Cortex-R5F with isolated safety MCU island
  • IO virtualization support
    • Peripheral Virtualization Unit (PVU) for low latency high bandwidth peripheral traffic
  • Multi-region firewall support for memory and peripheral isolation
  • Virtualization support with Ethernet, PCIe, and DMA

  • Device security (on select part numbers):

  • Secure boot with secure runtime support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 and IEC 61508 functional safety system design up to ASIL-D/SIL-3 targeted
    • Systematic capability up to ASIL-D/SIL-3 targeted
    • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
    • Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain
    • Hardware integrity up to ASIL-B/SIL-2 targeted for remainder of the Main Domain
    • FFI isolation provided between EMCU and the remainder of the Main Domain
    • Safety-related certification
      • ISO 26262 and IEC 61508 planned
  • AEC-Q100 qualified on part number variants ending in Q1

  • High-speed interfaces:

    • Integrated Ethernet TSN/AVB switch supporting up to 4 (DRA821U4) or 2 (DRA821U2) external ports:
      • One port supports 5Gb, 10Gb USXGMII/XFI
      • All ports support 2.5Gb SGMII
      • All ports support 1Gb SGMII/RGMII
      • DRA821U4: Any single port can support QSGMII (using all 4 internal ports)
      • Non-blocking wire-rate store and forward switch
      • InterVLAN (Layer3) routing support
      • Time synchronization support with IEEE 1588(annex D,E,F)
      • TSN/AVB support for traffic scheduling, shaping
      • Port mirroring feature for debug and diagnostics
      • Policing and rate limiting support
    • One RGMII/RMII port in safety MCU island
  • One PCI-Express Gen3 controller
    • Gen1, Gen2, and Gen3 operation with auto-negotiation
    • 4× lanes
  • One USB 3.1 Gen1 dual-role device subsystem
    • Supports type-C switching
    • Independently configurable as USB host, USB peripheral, or USB dual-role device

    Automotive interfaces:

  • Twenty CAN-FD ports
  • 12× Universal Asynchronous Receiver/Transmitter (UART)
  • 11× Serial Peripheral Interfaces (SPI)
  • One 8-channel ADC
  • 10× Inter-Integrated Circuit ( I2C™)
  • 2× Improved Inter-Integrated Circuit ( I3C)

    Audio interfaces:

  • 3× Multichannel Audio Serial Port (McASP) modules

    Flash memory interfaces:

  • Embedded Multi Media Card ( eMMC™ 5.1) interface
    • Support speeds of up to HS400
  • One Secure Digital 3.0/Secure Digital Input Output 3.0 (SD3.0/SDIO3.0) interfaces
  • One Octal SPI / Xccela™ / HyperBus™ Memory Controller (HBMC) interface
  • 16-nm FinFET technology
  • 17.2 mm x 17.2 mm, 0.8 mm pitch, IPC Class 3 PCB

Jacinto™ DRA821x processors, based on the Armv8 64-bit architecture, are optimized for gateway systems with cloud connectivity. The System-on-Chip (SoC) design reduces system-level costs and complexity through integration—notably, a system MCU, functional safety and security features, and an Ethernet switch for high-speed communication. Integrated diagnostics and functional safety features are targeted to ASIL-D and SIL 3 certification requirements. Real-time control and low-latency communication are enabled by a PCIe controller and a TSN capable Gigabit Ethernet switch.

Up to four general-purpose Arm® Cortex®-R5F subsystems can handle low-level, timing-critical processing tasks and leave the Arm® Cortex®-A72 core unencumbered for advanced and cloud-based applications.

Jacinto DRA821x processors also include the concept of the Extended MCU (eMCU) domain. This domain is a subset of the processors and peripherals on the main domain targeted at higher functional safety enablement, such as ASIL-D/SIL-3. The functional block diagram highlights which IP are included in the eMCU. For more details about eMCU and functional safety, see the DRA821 Safety Manual Processors Texas Instruments Jacinto™ 7 Family of Products (SPRUIX4).

Jacinto™ DRA821x processors, based on the Armv8 64-bit architecture, are optimized for gateway systems with cloud connectivity. The System-on-Chip (SoC) design reduces system-level costs and complexity through integration—notably, a system MCU, functional safety and security features, and an Ethernet switch for high-speed communication. Integrated diagnostics and functional safety features are targeted to ASIL-D and SIL 3 certification requirements. Real-time control and low-latency communication are enabled by a PCIe controller and a TSN capable Gigabit Ethernet switch.

Up to four general-purpose Arm® Cortex®-R5F subsystems can handle low-level, timing-critical processing tasks and leave the Arm® Cortex®-A72 core unencumbered for advanced and cloud-based applications.

Jacinto DRA821x processors also include the concept of the Extended MCU (eMCU) domain. This domain is a subset of the processors and peripherals on the main domain targeted at higher functional safety enablement, such as ASIL-D/SIL-3. The functional block diagram highlights which IP are included in the eMCU. For more details about eMCU and functional safety, see the DRA821 Safety Manual Processors Texas Instruments Jacinto™ 7 Family of Products (SPRUIX4).
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技術文件

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重要文件 類型 標題 格式選項 日期
* Data sheet DRA821 Jacinto™ Processors datasheet (Rev. E) PDF | HTML 2023年 6月 30日
* Errata J7200 DRA821 Silicon Revision 1.0, 2.0 (Rev. E) PDF | HTML 2024年 12月 1日
* User guide J7200 DRA821 Processor Silicon Revision 1.0 Technical Reference Manual (Rev. D) PDF | HTML 2024年 12月 13日
Functional safety information Confirmation of Software Component Qualification for JACINTO IPC for J721E, J721S2, J7200, J784S4, and J742S2 2026年 3月 19日
Application note Boot Flow Options on TDA4 Devices PDF | HTML 2026年 1月 5日
Functional safety information J721E, J721S2, J7200, J784S4, and J742S2 TÜV SÜD Letter of Confirmation for Software Component Qualification 2025年 10月 1日
Functional safety information J7200, J721E, J721S2, J722S, J742S2, and J784S4 SDL TÜV SÜD Functional Safety Certificate (Rev. A) 2025年 9月 25日
Functional safety information J721E, J721S2, J7200, J722S, J742S2, J784S4 MCAL TÜV SÜD Functional Safety Certificate (Rev. A) 2025年 9月 25日
Functional safety information TÜV SÜD Certificate for Functional Safety Software Development Process (Rev. D) 2025年 6月 17日
White paper 軟體定義車輛將汽車電子的未來推入正軌 (Rev. B) PDF | HTML 2025年 1月 29日
Application note Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. F) PDF | HTML 2024年 8月 5日
Application note Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design Guidelines (Rev. A) PDF | HTML 2024年 6月 4日
Application note MMC SW Tuning Algorithm (Rev. A) PDF | HTML 2024年 5月 14日
Application note Jacinto7 AM6x/TDA4x/DRA8x Schematic Checklist (Rev. B) PDF | HTML 2024年 4月 4日
Application note Jacinto7 HS Device Customer Return Process PDF | HTML 2023年 11月 16日
Application note Using TSN Ethernet Features to Improve Timing in Industrial Ethernet Controllers PDF | HTML 2023年 11月 15日
Application note UART Log Debug System on Jacinto 7 SoC PDF | HTML 2023年 1月 9日
Functional safety information Jacinto Functional Safety Enablers (Rev. A) PDF | HTML 2022年 12月 12日
User guide Powering DRA821 with TPS6594-Q1 and LP8764-Q1 (Rev. A) PDF | HTML 2022年 9月 12日
Application note How to Linux Fast Boot on DRA821U (Rev. A) PDF | HTML 2022年 7月 28日
Application note Dual-TDA4x System Solution PDF | HTML 2022年 4月 29日
Application note SPI Enablement & Validation on TDA4 Family PDF | HTML 2022年 4月 5日
Application note Enabling MAC2MAC Feature on Jacinto7 Soc 2022年 1月 10日
More literature Jacinto™ 7 automotive processors 2021年 12月 14日
Application note Jacinto 7 Display Subsystem Overview PDF | HTML 2021年 12月 10日
Application note Jacinto 7 Thermal Management Guide - Software Strategies PDF | HTML 2021年 12月 10日
User guide Single PMIC User's Guide for Jacinto 7 DRA821, PDN-2A PDF | HTML 2021年 11月 9日
Application note TISCI Server Integration in Vector AUTOSAR PDF | HTML 2021年 7月 16日
Application note TDA4 Flashing Techniques PDF | HTML 2021年 7月 8日
Application note J721E DDR Firewall Example PDF | HTML 2021年 7月 1日
Functional safety information Build safer, efficient, intelligent and autonomous robots 2021年 3月 4日
White paper Security Enablers on Jacinto™ 7 Processors 2021年 1月 4日
White paper Enabling Differentiation through MCU Integration on Jacinto™ 7 Processors 2020年 10月 22日
White paper 為下一代車輛開發的汽車閘道 (Rev. B) 2020年 10月 9日
Application note OSPI Tuning Procedure PDF | HTML 2020年 7月 8日

設計與開發

電源供應解決方案

為 DRA821U-Q1 尋找可用的電源供應解決方案。TI 提供適用於 TI 與非 TI 之系統單晶片 (SoC)、處理器、微控制器、感測器或現場可編程邏輯閘陣列 (FPGA) 的電源供應解決方案。

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開發板

J7200XSOMXEVM — DRA821系統模組

The J7200XSOMG01EVM system-on-module—when paired with the J721EXCP01EVM common processor board—lets you evaluate the DRA821 processor for networking applications throughout automotive and industrial markets. These processors perform particularly well in industrial and automotive gateway (...)

使用指南: PDF | HTML
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開發板

J721EXCPXEVM — 適用於 Jacinto™ 7 處理器的通用處理器電路板

適用於 Jacinto™ 7 處理器的 J721EXCP01EVM 通用處理器電路板，可讓您評估汽車與工業市場的視覺分析與網路應用。通用處理器電路板相容於所有 Jacinto 7 處理器系統模組（單獨出售或搭售），並且包含與輸入/輸出、JTAG 和各種擴充卡間的基本連線功能。

此多部分評估平台旨在降低整體評估成本、加快開發速度並縮短上市時間。

此 EVM 受處理器 SDK-Vision 支援，其中包含基礎驅動器、運算與視覺核心，以及範例應用架構與示範，可說明如何運用 Jacinto 7 處理器的強大異質架構。

使用指南: PDF | HTML
TI.com 無法提供
開發板

J7EXPCXEVM — 閘道/乙太網路交換器擴充卡

Expand the capabilities of the J721EXCP01EVM common processor board for evaluating Jacinto 7 processors in vision analytics and networking applications in automotive and industrial markets with our Gateway/Ethernet switch expansion card.

使用指南: PDF | HTML
TI.com 無法提供
偵錯探測器

TMDSEMU560V2STM-U — XDS560v2 System Trace USB 偵錯探測器

XDS560v2 是 XDS560™ 偵錯探測器系列的最高性能表現，支援傳統 JTAG 標準 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。請注意，序列線偵錯 (SWD) 不受支援。

所有 XDS 偵錯探測器均支援所有具有嵌入式追踪緩衝區 (ETB) 的 ARM 和 DSP 處理器中的核心和系統追蹤功能。對於針腳追蹤則需要 XDS560v2 PRO TRACE。

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (480Mbps) (...)

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偵錯探測器

LB-3P-TRACE32-ARM — 適用於 Arm® 架構微控制器和處理器的 Lauterbach TRACE32® 偵錯和追蹤系統

Lauterbach 的 TRACE32® 工具是一套先進的軟硬體元件，可讓開發人員分析、最佳化及認證各種 Arm® 架構微控制器和處理器。全球知名的嵌入式系統和 SoC 偵錯和追蹤解決方案是完美的解決方案，適用於從早期的矽前 (pre-silicon) 開發，到產品認證和現場故障排除等所有開發階段。Lauterbach 工具的直覺模組化設計為工程師提供現今最高的可用性能，以及可隨需求變化而調整和成長的系統。藉由 TRACE32® 偵錯器，開發人員也可透過單一偵錯介面，同時偵錯和控制 SoC 中的任何 C28x/C29x/C6x/C7x DSP 核心及所有其他 Arm (...)

從：Lauterbach GmbH
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軟體開發套件 (SDK)

PROCESSOR-SDK-J7200 — 適用 DRA821 Jacinto™ 處理器的軟體開發套件

Processor SDK RTOS (PSDK RTOS) can be used together with either Processor SDK Linux (PSDK Linux) or Processor SDK QNX (PSDK QNX) to form a multi-processor software development platform for DRA821 SoCs within TI’s Jacinto™ platform. The SDK provides a comprehensive set of software (...)
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IDE、配置、編譯器或偵錯程式

CCSTUDIO — CCStudio™ 整合式開發環境 (IDE)

CCStudio™ IDE 屬於 TI 廣泛的 CCStudio™ 開發工具生態系統。這是適用於 TI 微控制器、處理器、無線連線裝置和雷達感測器的整合式開發環境 (IDE)。它由一整套豐富的工具組成，可用於建立、除錯、分析及最佳化嵌入式應用程式。CCStudio IDE 支援 Windows®、Linux® 和 macOS® 平台。

CCStudio IDE 讓使用者能夠釋放 AI 的強大功能，協助嵌入式軟體開發。無論是初學者還是經驗豐富的專業人員，使用 AI 都可提升使用者的生產力，協助他們完成以往難以實現的任務。CCStudio IDE (...)

使用指南: PDF | HTML
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IDE、配置、編譯器或偵錯程式

DDR-CONFIG-J7200 — DDR Configuration Tool

This SysConfig based tool simplifies the process of configuring the DDR Subsystem Controller and PHY to interface to SDRAM devices. Based on the memory device, board design, and topology the tool outputs files to initialize and train the selected memory.
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支援產品和硬體
啟動
IDE、配置、編譯器或偵錯程式

SAFETI_CQKIT — 安全編譯器資格套件

開發安全編譯器資格認證套件是為了協助客戶對 TI ARM、C6000、C7000 或 C2000/CLA C/C++ 編譯器的使用進行認證，以確保符合功能安全標準，如 IEC 61508 和 ISO 26262。

安全編譯器資格認證套件：

  • 對 TI 客戶免費
  • 不需要使用者進行資格測試
  • 支援編譯器覆蓋範圍分析*
    • * 覆蓋範圍資料收集的說明可從每個 QKIT 下載頁面下載。
  • 不包括 Validas 諮詢

如需存取安全編譯器資格認證套件，請按一下上面其中一個索取按鈕。

如需進一步了解功能安全產品，請造訪 (...)

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IDE、配置、編譯器或偵錯程式

SYSCONFIG — Standalone desktop version of SysConfig

SysConfig is a configuration tool designed to simplify hardware and software configuration challenges to accelerate software development.

SysConfig is available as part of the Code Composer Studio™ integrated development environment as well as a standalone application. Additionally SysConfig (...)

支援產品和硬體

支援產品和硬體
啟動 下載選項
作業系統 (OS)

GHS-3P-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
從：Green Hills Software
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GHS-3P-UVELOSITY — Green Hills Software u-velOSity Safety RTOS

The µ-velOSity™ Safety RTOS is the smallest of Green Hills Software's real-time operating systems and was designed especially for microcontrollers. It supports a wide range of TI processor families using the Arm® Cortex-M or Cortex-R cores as a main CPU or as a co-processors (...)
從：Green Hills Software
造訪合作夥伴網站
作業系統 (OS)

QNX-3P-NEUTRINO-RTOS — QNX Neutrino RTOS

QNX Neutrino® 即時作業系統 (RTOS) 是一款功能完整且穩固的 RTOS，專為實現適用於汽車、醫療、運輸、軍事和工業嵌入式系統的新一代產品而設計。微核心設計與模組化架構，能讓客戶以低整體擁有成本打造高度最佳化且可靠的系統。
從：QNX Software Systems
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EXLFR-3P-ESYNC-OTA — 適用於軟體定義車輛的 Excelfore esync OTA 無線更新

Experience the future of the connected SDV starting with full vehicle OTA from Excelfore. The standardized and structured eSync pipeline securely scales to reach all the ECUs and smart sensors in the car, with the flexibility to cover any in-vehicle network topology or system architecture.
eSync (...)
從：ExcelFore
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EXLFR-3P-TSN — ExelFore's time sensitive network (TSN) automotive paths for safety-critical communications

軟體定義車輛 (SDV) 需要高性能網路、IP 定址和安全性，這些可透過乙太網路提供，但無法透過 CAN 提供。汽車應用也需要確保重要安全系統的延遲、頻寬和備援，這些是基本乙太網路無法提供的，但是 TSN 增加了這些功能。Excelfore 的 AVB/TSN 已通過 AVNU 認證。
乙太網路技術能以具成本效益的方式，將車內頻寬從 10MB 分支擴充至 10GB 以上。它還提供動態網路切換、網路安全性，而且能夠從雲端連線裝置。Excelfore 的 SOME/IP、DoIP、RTP、RTCP 和 UDS 通訊協定可將傳統系統帶入 SDV 時代，無縫整合至乙太網路骨幹，為 CAN (...)
從：ExcelFore
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VCTR-3P-MICROSAR — 適用於微控制器和高性能電腦 (HPC) 的 Vector MICROSAR AUTOSAR 軟體

MICROSAR 與 DaVinci 產品系列透過適用於微控制器與 HPC 的精密嵌入式軟體和強大開發工具，簡化 ECU 開發。有了先進的基礎架構軟體，您即可為 ECU 建立最佳基礎，並利用相關工具簡化所有相關開發作業。MICROSAR 嵌入式軟體是根據 AUTOSAR 經典和適應性等相關標準所開發。軟體也適合符合最高 ASIL D 之 ISO 26262 標準的安全相關應用。此外，智慧網路安全功能可保護控制單元免受未經授權的存取和竄改。Vector 涵蓋所有汽車與其他工業應用的使用案例。對於配備高性能電腦的軟體定義車輛 (SDV)，其可提供現代車輛作業系統，以做為開放式模組化軟體生態系統。
從：Vector Informatik GmbH
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模擬型號

J7200 DRA821 BSDL Model

SPRM776.ZIP (10 KB) - BSDL Model
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模擬型號

J7200 DRA821 IBIS Model

SPRM775.ZIP (2294 KB) - IBIS Model
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模擬型號

J7200 DRA821 Thermal Model

SPRM774.ZIP (185 KB) - Thermal Model
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FCBGA (ALM) 433 Ultra Librarian
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