TMS320F28P650SK

Name: TMS320F28P650SK
Brand: TI
SKU: TMS320F28P650SK
Price: 6.85 USD

現行

C2000 32 位元 MCU、400 MIPS、1xC28x + 1xCLA CPU、FPU64、1.28-MB 快閃記憶體、16-b ADC、Ethercat

立即訂購

產品規格表

document-pdfAcrobat TMS320F28P65x Real-Time Microcontrollers datasheet (Rev. B) (英文) PDF | HTML

使用指南

document-pdfAcrobat
TMS320F28P65x Real-Time Microcontrollers Technical Reference Manual (Rev. B) (英文)

勘誤表

document-pdfAcrobat
TMS320F28P65x Real-Time MCUs Silicon Errata (Rev. C) (英文)

TMS320F28P650SK

現行

產品規格表

立即訂購

產品詳細資料

CPU

C28x, CLA

Frequency (MHz)

200

Flash memory (kByte)

1280

RAM (kByte)

248

ADC resolution (bps)

12, 16

Total processing (MIPS)

400

Features

32-bit CPU timers, AES, Configurable logic block, Dual security zones, EtherCAT, FPU64, HRPWM, Lockstep, TMU, Watchdog timer

UART

CAN (#)

Sigma-delta filter

PWM (Ch)

TI functional safety category

Functional Safety-Compliant

Number of ADC channels

24, 34, 36, 40

SPI

QEP

USB

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Communication interface

CAN, CAN FD, EtherCAT, FSI, I2C, LIN, PMBUS, SCI, SPI, UART, USB

CPU

C28x, CLA

Frequency (MHz)

200

Flash memory (kByte)

1280

RAM (kByte)

248

ADC resolution (bps)

12, 16

Total processing (MIPS)

400

Features

32-bit CPU timers, AES, Configurable logic block, Dual security zones, EtherCAT, FPU64, HRPWM, Lockstep, TMU, Watchdog timer

UART

CAN (#)

Sigma-delta filter

PWM (Ch)

TI functional safety category

Functional Safety-Compliant

Number of ADC channels

24, 34, 36, 40

SPI

QEP

USB

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Communication interface

CAN, CAN FD, EtherCAT, FSI, I2C, LIN, PMBUS, SCI, SPI, UART, USB

HLQFP (PTP)

176

676 mm² 26 x 26

HTQFP (PZP)

100

256 mm² 16 x 16

NFBGA (NMR)

169

81 mm² 9 x 9

NFBGA (ZEJ)

256

169 mm² 13 x 13

Real-time Processing

Contains up to three CPUs: two 32-bit C28x DSP CPUs and one CLA CPU, all running at 200 MHz
Delivers a total processing power equivalent to 1000-MHz Arm Cortex-M7 based device on real-time signal chain performance (see the Real-time Benchmarks Showcasing C2000™ Control MCU’s Optimized Signal Chain Application Note)
C28x DSP architecture
- IEEE 754 double-precision (64-bit) Floating-Point Unit (FPU)
- Trigonometric Math Unit (TMU)
- Fast Integer Division (FINTDIV)
- CRC engine and instructions (VCRC)
Control Law Accelerator (CLA) CPU
- IEEE 754 single-precision floating-point
- Executes code independently of C28x CPUs

Memory

1.28MB of CPU-mappable flash (ECC-protected) with 5 flash banks
248KB of RAM (Enhanced Parity-protected)
External Memory Interface (EMIF) with ASRAM, SDRAM support or ASIC/FPGA

Analog Subsystem

Three Analog-to-Digital Converters (ADCs)
- 16-bit mode, 1.19 MSPS each
- 12-bit mode, 3.92 MSPS each
- Up to 40 single-ended or 19 differential inputs
- Separate sample-and-hold (S/H) on each ADC to enable simultaneous measurements
- Hardware post-processing of conversions
- Hardware oversampling (up to 128x) and undersampling modes, with accumulation, averaging and outlier rejection
- 24 redundant input channels for flexibility
- Automatic comparison of conversion results for functional safety applications
11 windowed comparators with 12-bit Digital-to-Analog Converter (DAC) references
- DAC with slope compensation – enabling peak current and valley current mode control
- Connection options for internal temperature sensor and ADC reference
Two 12-bit buffered DAC outputs

Control Peripherals

36 Pulse Width Modulator (PWM) channels, all with 150-ps high-resolution capability (HRPWM)
- Minimum Dead-Band Logic (MINDB), Illegal Combo Logic (ICL), and other special features (that is, Diode Emulation [DE]) support
- Enable Matrix Converters, Multilevel Converters, and Resonant Converters support without additional external logic
Seven Enhanced Capture (eCAP) modules
- High-resolution Capture (HRCAP) available on two of the seven eCAP modules
- Two new monitor units for edge, pulse width, and period that can be coupled with ePWM strobes and trip events
- Increased 256 inputs for more capture options
- New ADC SOC generation capability
- eCAP can also be used for additional PWM
- Six Enhanced Quadrature Encoder Pulse (eQEP) modules
- 16 Sigma-Delta Filter Module (SDFM) input channels, 2 independent filters per channel
- Embedded Pattern Generator (EPG)
Configurable Logic Block
- Six logic tiles to augment existing peripheral capability or define customized logic to reduce or remove external CPLD/FPGA
- Supports Encoder interfaces without the need of FPGA
- Enables customized PWM generation for power conversion

Communications Peripherals

EtherCAT SubordinateDevice (or SubDevice) Controller (ESC)
USB 2.0 (MAC + PHY)
Fast Serial Interface (FSI) enabling up to 200Mbps data exchange across isolation
Four high-speed (up to 50-MHz) SPI ports
Four Serial Communications Interfaces (SCI) (support UART)
Two high-speed (25Mbps) Universal Asynchronous Receiver/Transmitters (UARTs)
Two I2C interfaces (400Kbps)
External boot option via SPI/ SCI/I2C
Two UART-compatible Local Interconnect Network (LIN) Modules (support SCI)
Power-Management Bus (PMBus) interface (supports I2C)
One Controller Area Network (CAN/DCAN)
Two CAN FD/MCAN Controller Area Networks with Flexible Data Rate

System Peripherals

Two 6-channel Direct Memory Access (DMA) controllers
185 individually programmable multiplexed General-Purpose Input/Output (GPIO) pins
Expanded Peripheral Interrupt controller (ePIE)
Low-power mode (LPM) support
Embedded Real-time Analysis and Diagnostic (ERAD)
Background CRC (BGCRC)

Security Peripherals

Advanced Encryption Standard (AES-128, 192, 256) accelerator
Security
- JTAGLOCK
- Zero-pin boot
- Dual-zone security
Unique Identification (UID) number

Safety Peripherals

Easier implementation with Reciprocal comparison
Lockstep on C28x CPU 2
Memory Power-On Self-Test (MPOST)
Hardware Built-in Self-Test (HWBIST)
Functional Safety-Compliant targeted
- Developed for functional safety applications
- Documentation will be available to aid ISO 26262 and IEC 61508 system design
- Systematic capability up to ASIL D and SIL 3 targeted
- Hardware capability up to ASIL B and SIL 2 targeted
Safety-related certification
- ISO 26262 and IEC 61508 certification up to ASIL B and SIL 2 by TÜV SÜD planned

Clock and System Control

Two internal 10-MHz oscillators
On-chip crystal oscillator
2*APLL, BOR, Redundant interrupt vector RAM
Windowed watchdog timer module
Missing clock detection circuitry
Dual-clock Comparator (DCC)
Live Firmware Update (LFU)
- Fast context switching from old to new firmware with or without a power cycle
1.2-V core, 3.3-V I/O design
- Internal VREG for 1.2-V generation
- Brownout reset (BOR) circuit

Package options:

Lead-free, green packaging
256-ball New Fine Pitch Ball Grid Array (nFBGA) [ZEJ suffix], 13 mm × 13 mm/0.8-mm pitch
176-pin PowerPAD™ Thermally Enhanced Low-profile Quad Flatpack (HLQFP) [PTP suffix], 26 mm × 26 mm/0.5-mm pitch
169-ball New Fine Pitch Ball Grid Array (nFBGA) [NMR suffix], 9 mm × 9 mm/0.65-mm pitch
100-pin PowerPAD™ Thermally Enhanced Thin Quad Flatpack (HTQFP) [PZP suffix], 16 mm × 16 mm/0.5-mm pitch

Temperature

Ambient (T A ): –40°C to 125°C (industrial and automotive qualified)

Real-time Processing

Contains up to three CPUs: two 32-bit C28x DSP CPUs and one CLA CPU, all running at 200 MHz
Delivers a total processing power equivalent to 1000-MHz Arm Cortex-M7 based device on real-time signal chain performance (see the Real-time Benchmarks Showcasing C2000™ Control MCU’s Optimized Signal Chain Application Note)
C28x DSP architecture
- IEEE 754 double-precision (64-bit) Floating-Point Unit (FPU)
- Trigonometric Math Unit (TMU)
- Fast Integer Division (FINTDIV)
- CRC engine and instructions (VCRC)
Control Law Accelerator (CLA) CPU
- IEEE 754 single-precision floating-point
- Executes code independently of C28x CPUs

Memory

1.28MB of CPU-mappable flash (ECC-protected) with 5 flash banks
248KB of RAM (Enhanced Parity-protected)
External Memory Interface (EMIF) with ASRAM, SDRAM support or ASIC/FPGA

Analog Subsystem

Three Analog-to-Digital Converters (ADCs)
- 16-bit mode, 1.19 MSPS each
- 12-bit mode, 3.92 MSPS each
- Up to 40 single-ended or 19 differential inputs
- Separate sample-and-hold (S/H) on each ADC to enable simultaneous measurements
- Hardware post-processing of conversions
- Hardware oversampling (up to 128x) and undersampling modes, with accumulation, averaging and outlier rejection
- 24 redundant input channels for flexibility
- Automatic comparison of conversion results for functional safety applications
11 windowed comparators with 12-bit Digital-to-Analog Converter (DAC) references
- DAC with slope compensation – enabling peak current and valley current mode control
- Connection options for internal temperature sensor and ADC reference
Two 12-bit buffered DAC outputs

Control Peripherals

36 Pulse Width Modulator (PWM) channels, all with 150-ps high-resolution capability (HRPWM)
- Minimum Dead-Band Logic (MINDB), Illegal Combo Logic (ICL), and other special features (that is, Diode Emulation [DE]) support
- Enable Matrix Converters, Multilevel Converters, and Resonant Converters support without additional external logic
Seven Enhanced Capture (eCAP) modules
- High-resolution Capture (HRCAP) available on two of the seven eCAP modules
- Two new monitor units for edge, pulse width, and period that can be coupled with ePWM strobes and trip events
- Increased 256 inputs for more capture options
- New ADC SOC generation capability
- eCAP can also be used for additional PWM
- Six Enhanced Quadrature Encoder Pulse (eQEP) modules
- 16 Sigma-Delta Filter Module (SDFM) input channels, 2 independent filters per channel
- Embedded Pattern Generator (EPG)
Configurable Logic Block
- Six logic tiles to augment existing peripheral capability or define customized logic to reduce or remove external CPLD/FPGA
- Supports Encoder interfaces without the need of FPGA
- Enables customized PWM generation for power conversion

Communications Peripherals

EtherCAT SubordinateDevice (or SubDevice) Controller (ESC)
USB 2.0 (MAC + PHY)
Fast Serial Interface (FSI) enabling up to 200Mbps data exchange across isolation
Four high-speed (up to 50-MHz) SPI ports
Four Serial Communications Interfaces (SCI) (support UART)
Two high-speed (25Mbps) Universal Asynchronous Receiver/Transmitters (UARTs)
Two I2C interfaces (400Kbps)
External boot option via SPI/ SCI/I2C
Two UART-compatible Local Interconnect Network (LIN) Modules (support SCI)
Power-Management Bus (PMBus) interface (supports I2C)
One Controller Area Network (CAN/DCAN)
Two CAN FD/MCAN Controller Area Networks with Flexible Data Rate

System Peripherals

Two 6-channel Direct Memory Access (DMA) controllers
185 individually programmable multiplexed General-Purpose Input/Output (GPIO) pins
Expanded Peripheral Interrupt controller (ePIE)
Low-power mode (LPM) support
Embedded Real-time Analysis and Diagnostic (ERAD)
Background CRC (BGCRC)

Security Peripherals

Advanced Encryption Standard (AES-128, 192, 256) accelerator
Security
- JTAGLOCK
- Zero-pin boot
- Dual-zone security
Unique Identification (UID) number

Safety Peripherals

Easier implementation with Reciprocal comparison
Lockstep on C28x CPU 2
Memory Power-On Self-Test (MPOST)
Hardware Built-in Self-Test (HWBIST)
Functional Safety-Compliant targeted
- Developed for functional safety applications
- Documentation will be available to aid ISO 26262 and IEC 61508 system design
- Systematic capability up to ASIL D and SIL 3 targeted
- Hardware capability up to ASIL B and SIL 2 targeted
Safety-related certification
- ISO 26262 and IEC 61508 certification up to ASIL B and SIL 2 by TÜV SÜD planned

Clock and System Control

Two internal 10-MHz oscillators
On-chip crystal oscillator
2*APLL, BOR, Redundant interrupt vector RAM
Windowed watchdog timer module
Missing clock detection circuitry
Dual-clock Comparator (DCC)
Live Firmware Update (LFU)
- Fast context switching from old to new firmware with or without a power cycle
1.2-V core, 3.3-V I/O design
- Internal VREG for 1.2-V generation
- Brownout reset (BOR) circuit

Package options:

Lead-free, green packaging
256-ball New Fine Pitch Ball Grid Array (nFBGA) [ZEJ suffix], 13 mm × 13 mm/0.8-mm pitch
176-pin PowerPAD™ Thermally Enhanced Low-profile Quad Flatpack (HLQFP) [PTP suffix], 26 mm × 26 mm/0.5-mm pitch
169-ball New Fine Pitch Ball Grid Array (nFBGA) [NMR suffix], 9 mm × 9 mm/0.65-mm pitch
100-pin PowerPAD™ Thermally Enhanced Thin Quad Flatpack (HTQFP) [PZP suffix], 16 mm × 16 mm/0.5-mm pitch

Temperature

Ambient (T A ): –40°C to 125°C (industrial and automotive qualified)

The TMS320F28P65x (F28P65x) is a member of the C2000™ real-time microcontroller family of scalable, ultra-low latency devices designed for efficiency in power electronics, including but not limited to: high power density, high switching frequencies, and supporting the use of IGBT, GaN, and SiC technologies.

These include such applications as:

The real-time control subsystem is based on TI’s 32-bit C28x DSP core, which provides 200 MIPS of signal-processing performance in each core for floating- or fixed-point code running from either on-chip flash or SRAM. This is equivalent to the 400-MHz processing power on a Cortex®-M7 based device (C28x DSP core gives two times more performance than the Cortex®-M7 core).The C28x CPU is further boosted by the Trigonometric Math Unit (TMU) and VCRC (Cyclical Redundancy Check) extended instruction sets, speeding up common algorithms key to real-time control systems. Extended instruction sets enable IEEE double-precision 64-bit floating-point math. Finally, the Control Law Accelerator (CLA) enables an additional 200 MIPS per core of independent processing ability. This is equivalent to the 280-MHz processing power on a Cortex®-M7 based device (CLA CPU gives 40% more performance than the Cortex®-M7 core).

The lockstep dual-CPU comparator option has been added in the secondary C28x CPU along with ePIE and DMA for detection of permanent and transient faults. To allow fast context switching from existing to new firmware, hardware enhancements for Live Firmware Update (LFU) have been added to F28P65x.

High-performance analog blocks are tightly integrated with the processing and control units to provide optimal real-time signal chain performance. The Analog-to-Digital Converter (ADC) has been enhanced with up to 40 analog channels, 22 of which have general-purpose input/output (GPIO) capability. Implementation of oversampling is greatly simplified with hardware improvement. For safety-critical ADC conversions, a hardware redundancy checker has been added that provides the ability to compare ADC conversion results from multiple ADC modules for consistency without additional CPU cycles. Thirty-six frequency-independent PWMs, all with high-resolution capability, enable control of multiple power stages, from 3-phase inverters to advanced multilevel power topologies. The PWMs have been enhanced with Minimum Dead-Band Logic (MINDL) and Illegal Combo Logic (ICL) features.

The inclusion of the Configurable Logic Block (CLB) allows the user to add custom logic and potentially integrate FPGA-like functions into the C2000 real-time MCU.

An EtherCAT SubDevice Controller and other industry-standard protocols like CAN FD and USB 2.0 are available on this device. The Fast Serial Interface (FSI) enables up to 200 Mbps of robust communications across an isolation boundary.

As a highly connected device, the F28P65x also offers various security enablers to help designers implement their cyber security strategy and support features like hardware encryption, secure JTAG and secure Boot.

From a safety standpoint, F28P65x supports numerous safety enablers. For more details, see Industrial Functional Safety for C2000™ Real-Time Microcontrollers and Automotive Functional Safety for C2000™ Real-Time Microcontrollers.

Want to learn more about features that make C2000 MCUs the right choice for your real-time control system? Check out The Essential Guide for Developing With C2000™ Real-Time Microcontrollers and visit the C2000™ real-time control MCUs page.

The Getting Started With C2000™ Real-Time Control Microcontrollers (MCUs) Getting Started Guide covers all aspects of development with C2000 devices from hardware to support resources. In addition to key reference documents, each section provides relevant links and resources to further expand on the information covered.

Ready to get started? Check out the TMDSCNCD28P65X evaluation board and download C2000Ware.

These include such applications as:

The inclusion of the Configurable Logic Block (CLB) allows the user to add custom logic and potentially integrate FPGA-like functions into the C2000 real-time MCU.

Ready to get started? Check out the TMDSCNCD28P65X evaluation board and download C2000Ware.

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	類型	標題		日期
*	Data sheet	TMS320F28P65x Real-Time Microcontrollers datasheet (Rev. B)	PDF \| HTML	2023年 11月 17日
*	Errata	TMS320F28P65x Real-Time MCUs Silicon Errata (Rev. C)	PDF \| HTML	2024年 3月 19日
*	User guide	TMS320F28P65x Real-Time Microcontrollers Technical Reference Manual (Rev. B)	PDF \| HTML	2024年 8月 20日
	Application note	Digital Control Implementation for Hybrid Hysteretic Control LLC Converter (Rev. A)	PDF \| HTML	2024年 8月 21日
	Application note	Development Tool Versions for C2000™ Support (Rev. A)	PDF \| HTML	2024年 6月 26日
	Product overview	Implementing IEC 60730 / UL 1998 Compliance for C2000 Real-Time Microcontrollers (Rev. A)	PDF \| HTML	2024年 6月 25日
	Product overview	Industrial Functional Safety for C2000™ Real-Time Microcontrollers (Rev. E)		2024年 6月 3日
	Application note	Obtain UL/IEC 60730-1/60335-1 Class B Certification Based on C2000™ MCU Diagnostic Library in Appliances	PDF \| HTML	2024年 5月 30日
	Functional safety information	Functional Safety Manual for TMS320F28P65x Real-Time Microcontrollers	PDF \| HTML	2024年 5月 29日
	Functional safety information	TMS320F28P65x TUV SUD Functional Safety Certificate		2024年 5月 29日
	Application note	EEPROM Emulation for Generation 3 C2000 Real-Time Controllers (Rev. A)	PDF \| HTML	2024年 4月 12日
	User guide	C2000 Real-Time Control Peripheral Reference Guide (Rev. S)	PDF \| HTML	2024年 4月 5日
	Application note	Clock Edge Delay Compensation With Isolated Modulators Digital Interface to MCUs (Rev. A)	PDF \| HTML	2024年 1月 12日
	Application note	EEPROM Emulation for Gen 3 C2000 Real-Time MCUs	PDF \| HTML	2023年 11月 16日
	Cybersecurity advisory	C2000 DCSM ROM Gadget/ROP Vulnerability	PDF \| HTML	2023年 11月 13日
	User guide	Migration Between TMS320F2837x and TMS320F28P65x	PDF \| HTML	2023年 8月 2日
	User guide	Migration Between TMS320F2838x and TMS320F28P65x	PDF \| HTML	2023年 7月 31日
	White paper	Achieving High Efficiency and Enabling Integration in EV Powertrain Subsystems (Rev. A)	PDF \| HTML	2023年 7月 17日
	Application note	CRC Engines in C2000 Devices (Rev. A)	PDF \| HTML	2023年 5月 1日
	Application note	Migrating Software From 8-Bit (Byte) Addressable CPU’s to C28x CPU (Rev. A)	PDF \| HTML	2023年 4月 19日
	Application note	ADC Input Circuit Evaluation for C2000 MCUs (using TINA-TI simulation tool) (Rev. A)	PDF \| HTML	2023年 3月 24日
	Application note	ADC Input Circuit Evaluation for C2000 Real-Time MCUs (using PSPICE-FOR-TI)	PDF \| HTML	2023年 3月 24日
	Application note	Charge-Sharing Driving Circuits for C2000 ADCs (using PSPICE-FOR-TI) (Rev. A)	PDF \| HTML	2023年 3月 24日
	Application note	Charge-Sharing Driving Circuits for C2000 ADCs (using TINA-TI simulation tool) (Rev. A)	PDF \| HTML	2023年 3月 24日
	Application note	Methods for Mitigating ADC Memory Cross-Talk (Rev. A)	PDF \| HTML	2023年 3月 24日
	Application note	Using SMI of C2000 EtherCAT Slave Controller for Ethernet PHY Configuration	PDF \| HTML	2023年 2月 27日
	Application note	C2000 ePWM Developer’s Guide (Rev. A)	PDF \| HTML	2023年 2月 24日
	Application note	How to Implement Custom Serial Interfaces Using Configurable Logic Block (CLB)	PDF \| HTML	2023年 2月 3日
	Application note	C2000 SysConfig Linker Command Tool	PDF \| HTML	2023年 1月 26日
	Application note	Using the Fast Serial Interface (FSI) With Multiple Devices in an Application (Rev. E)	PDF \| HTML	2023年 1月 25日
	Application note	Diagnosing Delta-Sigma Modulator Bitstream Using C2000™ Configurable Logic Block	PDF \| HTML	2022年 12月 19日
	Application note	Software Examples to Showcase Unique Capabilities of TI’s C2000™ CLA (Rev. A)	PDF \| HTML	2022年 11月 17日
	User guide	Getting Started With C2000™ Real-Time Control Microcontrollers (MCUs) (Rev. C)	PDF \| HTML	2022年 6月 29日
	Application note	Implement three-phase interleaved LLC on C2000 Type-4 PWM	PDF \| HTML	2022年 3月 30日
	Application note	The Essential Guide for Developing With C2000 Real-Time Microcontrollers (Rev. F)	PDF \| HTML	2022年 3月 3日
	Application note	Real-Time Benchmarks Showcasing C2000™ Control MCU's Optimized Signal Chain (Rev. A)	PDF \| HTML	2021年 12月 15日
	Application note	Achieve Delayed Protection for Three-Level Inverter With Type 4 EPWM	PDF \| HTML	2021年 10月 29日
	Application note	C2000 SysConfig	PDF \| HTML	2021年 10月 20日
	Application note	Getting Started with the MCAN (CAN FD) Module	PDF \| HTML	2021年 10月 20日
	Application note	Achieve Delayed Protection for Three-Level Inverter With CLB	PDF \| HTML	2021年 6月 28日
	Application note	Programming Examples for the DCAN Module (Rev. A)	PDF \| HTML	2021年 5月 20日
	Application note	Leverage New Type ePWM Features for Multiple Phase Control	PDF \| HTML	2021年 5月 11日
	Application note	C2000™ DCSM Security Tool (Rev. A)	PDF \| HTML	2021年 5月 10日
	White paper	結合 TI GaN FETs 與 C2000™ 即時 MCU，實現功率密集與有效率的數位電源系統		2021年 3月 18日
	Application note	CRM/ZVS PFC Implementation Based on C2000 Type-4 PWM Module	PDF \| HTML	2021年 2月 18日
	More literature	Maximize density, power, and reliability with TI GaN and C2000™ real-time MCUs		2020年 12月 15日
	Application note	C2000™ Unique Device Number (Rev. B)	PDF \| HTML	2020年 9月 17日
	Application note	Secure BOOT On C2000 Device		2020年 7月 21日
	Application note	How to Migrate Custom Logic From an FPGA/CPLD to C2000 Microcontrollers (Rev. A)		2020年 6月 15日
	Application note	Enhancing Device Security by Using JTAGLOCK Feature	PDF \| HTML	2020年 5月 27日
	Application note	EtherCAT Based Connected Servo Drive using Fast Current Loop on PMSM (Rev. B)	PDF \| HTML	2020年 2月 19日
	White paper	Distributed Power Control Architecture w/ C2000 MCUs Over Fast Serial Interface	PDF \| HTML	2020年 2月 14日
	E-book	E-book: An engineer’s guide to industrial robot designs		2020年 2月 12日
	Application note	Configurable Error Generator for Controller Area Network	PDF \| HTML	2019年 12月 19日
	User guide	TMS320C28x Extended Instruction Sets Technical Reference Manual (Rev. C)		2019年 10月 29日
	Application note	Leveraging High Resolution Capture (HRCAP) for Single Wire Data Transfer	PDF \| HTML	2019年 8月 28日
	Application note	Fast Integer Division – A Differentiated Offering From C2000 Product Family	PDF \| HTML	2019年 6月 14日
	Application note	Calculating Useful Lifetimes of Embedded Processors (Rev. B)	PDF \| HTML	2019年 5月 7日
	Application note	Embedded Real-Time Analysis and Response for Control Applications	PDF \| HTML	2019年 3月 29日
	Application note	Designing With The C2000 Configurable Logic Block		2019年 2月 5日
	Application note	MSL Ratings and Reflow Profiles (Rev. A)		2018年 12月 13日
	Application note	Fast Serial Interface (FSI) Skew Compensation		2018年 11月 8日
	White paper	Maximizing power for Level 3 EV charging stations		2018年 6月 12日
	User guide	TMS320C28x DSP CPU and Instruction Set (Rev. F)		2015年 4月 10日
	Application note	Calculating FIT for a Mission Profile		2015年 3月 24日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

LAUNCHXL-F28P65X — C2000™ 即時 MCU F28P65x LaunchPad™ 開發套件

LAUNCHXL-F28P65X 是適用 TI C2000™ 即時微控制器 F28P65x 產品系列的低成本開發電路板。最適合初始評估與原型設計，提供標準化且使用方便的平台，可讓您開發下一個應用程式。此擴充版本 LaunchPad™ 開發套件提供額外接腳可用於開發，並支援兩個 BoosterPack™ 外掛程式模組連接。屬於 TI MCU LaunchPad 龐大生態系統的一部分，也與各種外掛程式模組交互相容。

使用指南: PDF | HTML

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軟體開發套件 (SDK)

C2000WARE — C2000Ware for C2000 Microcontrollers

C2000Ware is a cohesive set of software and documentation created to minimize development time. It includes device-specific drivers, libraries, and peripheral examples.

Hardware design schematics, BOM, gerber files, and documentation for C2000 controlCARDS, Experimenter Kits, and LaunchPads.
(...)

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TMS320F2800153-Q1 — 具有 HRPWM、CAN-FD、鎖階 ASIL B 的車用 C2000™ 32 位元 MCU 120-MHz 64-KB 快閃記憶體

TMS320F2800154-Q1 — 具有 CAN-FD、鎖階 ASIL B 的車用 C2000™ 32 位元 MCU 100-MHz 128-KB 快閃記憶體

TMS320F2800155 — 具 HRPWM、CAN-FD 的 C2000™ 32 位元 MCU 120-MHz 128-KB 快閃記憶體

TMS320F2800155-Q1 — 具有 HRPWM、CAN-FD、鎖階 ASIL B 的車用 C2000™ 32 位元 MCU 120-MHz 128-KB 快閃記憶體

TMS320F2800156-Q1 — 具有 CAN-FD、鎖階 ASIL B、0 和 1 級的車用 C2000™ 32 位元 MCU 100-MHz 256-KB 快閃記憶體

TMS320F2800157 — 具 HRPWM、CAN-FD 的 C2000™ 32 位元 MCU 120-MHz 256-KB 快閃記憶體

TMS320F2800157-Q1 — 具有 HRPWM、CAN-FD、鎖階 ASIL B、0 和 1 級的車用 C2000™ 32 位元 MCU 120-MHz 256-KB 快閃記憶體

TMS320F28P550SJ — C2000™ 32 位元 MCU、1x C28x + 1x CLA、150-MHz、1.1-MB 快閃記憶體、5x ADC、CLB、AES 和 NPU

TMS320F28P559SJ-Q1 — 車用 C2000™ 32 位元 MCU、1x C28x + 1x CLA、150-MHz、1.1-MB 快閃記憶體、5x ADC、CLB、AES 和 NNPU

TMS320F28P650DH — C2000 32-bit MCU, 600 MIPS, 2xC28x + 1xCLA CPU, FPU64, 768kB flash, 16-b ADC

TMS320F28P650DK — C2000 ™ 32 位 MCU ， 2x C28x +CLA CPU ，鎖定步驟， 1.28-MB 快閃記憶體， 16-b ADC ， HRPWM ， EtherCAT ， CAN-FD ， AES

TMS320F28P650SH — C2000 32 位元 MCU、400 MIPS、1xC28x + 1xCLA CPU、FPU64、768kB 快閃記憶體、16-b ADC

TMS320F28P650SK — C2000 32 位元 MCU、400 MIPS、1xC28x + 1xCLA CPU、FPU64、1.28-MB 快閃記憶體、16-b ADC、Ethercat

TMS320F28P659DH-Q1 — Automotive C2000 32-bit MCU, 600 MIPS, 2xC28x + 1xCLA + Lockstep, FPU64, 768kB flash, 16-b ADC

TMS320F28P659DK-Q1 — C2000™ 32 位元 MCU、2x C28x+CLA CPU、鎖階、1.28-MB 快閃記憶體、16-b ADC、HRPWM、CAN-FD、AES

TMS320F28P659SH-Q1 — Automotive C2000 32-bit MCU, 400 MIPS, 1xC28x + 1xCLA , FPU64, 768kB flash, 16-b ADC

硬體開發

開發板

LAUNCHXL-F2800157 — C2000™ 即時 MCU F2800157 LaunchPad™ 開發套件

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軟體開發套件 (SDK)

C2000WARE-MOTORCONTROL-SDK — MotorControl software development kit (SDK) for C2000™ MCUs

MotorControl SDK for C2000™ microcontrollers (MCU) is a cohesive set of software infrastructure, tools, and documentation designed to minimize C2000 real-time controller based motor control system development time targeted for various three-phase motor control applications. The software (...)