TDA2P-ABZ

Name: TDA2P-ABZ
Brand: TI
SKU: TDA2P-ABZ

現行

適用於 ADAS 且具有繪圖、成像、視訊和視覺加速選項的 TDA2 腳位相容 SoC 系列

立即訂購

產品規格表

document-pdfAcrobat TDA2Px ADAS Applications Processor 23mm Package (ABZ Package) Silicon Revision 1.0 datasheet (Rev. F) (英文) PDF | HTML

勘誤表

document-pdfAcrobat
TDA2Px Silicon Errata (Rev. B) (英文)

TDA2P-ABZ

現行

產品規格表

立即訂購

產品詳細資料

Arm CPU

2 Arm Cortex-A15

Arm (max) (MHz)

500, 650, 750, 1176

CPU

32-bit

Graphics acceleration

1 2D, 2 3D

Display type

1 HDMI, 3 LCD

Protocols

Ethernet

Ethernet MAC

2-Port 1Gb switch

PCIe

2 PCIe Gen 3

Hardware accelerators

1 Image Subsystem Processor, 1 Image Video Accelerator, 2 Embedded Vision Engines (EVE)

Features

Vision Analytics

Operating system

Android, Linux, RTOS

Security

Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection

Rating

Automotive

Operating temperature range (°C)

-40 to 125

Arm CPU

2 Arm Cortex-A15

Arm (max) (MHz)

500, 650, 750, 1176

CPU

32-bit

Graphics acceleration

1 2D, 2 3D

Display type

1 HDMI, 3 LCD

Protocols

Ethernet

Ethernet MAC

2-Port 1Gb switch

PCIe

2 PCIe Gen 3

Hardware accelerators

1 Image Subsystem Processor, 1 Image Video Accelerator, 2 Embedded Vision Engines (EVE)

Features

Vision Analytics

Operating system

Android, Linux, RTOS

Security

Cryptography, Debug security, Device identity, Isolation firewalls, Secure boot, Secure storage & programming, Software IP protection

Rating

Automotive

Operating temperature range (°C)

-40 to 125

FCCSP (ABZ)

760

529 mm² 23 x 23

Architecture Designed for ADAS Applications
Video, Image, and Graphics Processing Support
- Full-HD Video (1920 × 1080p, 60 fps)
- Multiple Video Input and Video Output
Dual Arm^® Cortex^®-A15 Microprocessor Subsystem
Up to Two C66x Floating-Point VLIW DSP
- Fully Object-Code Compatible with C67x and C64x+
- Up to Thirty-Two 16 × 16-Bit Fixed-Point Multiplies per Cycle
Up to 2.5MB of On-Chip L3 RAM
Level 3 (L3) and Level 4 (L4) Interconnects
Two DDR2/DDR3/DDR3L Memory Interface (EMIF) Modules
- Supports up to DDR2-800 and DDR3-1333
- Up to 2GB Supported per EMIF
Dual Arm® Cortex®-M4 Image Processing Units (IPU)
Vision AccelerationPac
- Up to Two Embedded Vision Engines (EVEs)
Imaging Subsystem (ISS)
- Image Signal Processor (ISP)
- Wide Dynamic Range and Lens Distortion Correction (WDR and Mesh LDC)
- One Camera Adaptation Layer (CAL_B)
IVA-HD Subsystem
Display Subsystem
- Display Controller with DMA Engine and up to Three Pipelines
- HDMI™ Encoder: HDMI 1.4a and DVI 1.0 Compliant
2D-Graphics Accelerator (BB2D) Subsystem
- Vivante^® GC320 Core
Video Processing Engine (VPE)
Dual-Core PowerVR^® SGX544 3D GPU
Two Video Input Port (VIP) Modules
- Support for up to Eight Multiplexed Input Ports
General-Purpose Memory Controller (GPMC)
Enhanced Direct Memory Access (EDMA) Controller
2-Port Gigabit Ethernet (GMAC)
Up to Two Controller Area Network (DCAN) Modules
- CAN 2.0B Protocol
Modular Controller Area Network (MCAN) Module
- CAN 2.0B Protocol with Available FD (Flexible Data Rate) Functionality
PCI Express^® 3.0 Port with Integrated PHY
- One 2-Lane Gen2-Compliant Port
- or Two 1-Lane Gen2-Compliant Ports
Sixteen 32-Bit General-Purpose Timers
32-Bit MPU Watchdog Timer
Ten Configurable UART/IrDA/CIR Modules
Four Multichannel Serial Peripheral Interfaces (McSPI)
Quad SPI Interface
Five Inter-Integrated Circuit (I²C) Ports
SATA Interface
Eight Multichannel Audio Serial Port (McASP) Modules
SuperSpeed USB 3.0 Dual-Role Device
Three High-Speed USB 2.0 Dual-Role Devices
Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD^®/SDIO)
Up to 247 General-Purpose I/O (GPIO) Pins
Real-Time Clock Subsystem (RTCSS)
Device Security Features
- Hardware Crypto Accelerators and DMA
- Firewalls
- JTAG^® Lock
- Secure Keys
- Secure ROM and Boot
- Customer Programmable Keys and OTP Data
Power, Reset, and Clock Management
On-Chip Debug With CTools Technology
Automotive AEC-Q100 Qualified
28-nm CMOS Technology
23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABZ)

Architecture Designed for ADAS Applications
Video, Image, and Graphics Processing Support
- Full-HD Video (1920 × 1080p, 60 fps)
- Multiple Video Input and Video Output
Dual Arm^® Cortex^®-A15 Microprocessor Subsystem
Up to Two C66x Floating-Point VLIW DSP
- Fully Object-Code Compatible with C67x and C64x+
- Up to Thirty-Two 16 × 16-Bit Fixed-Point Multiplies per Cycle
Up to 2.5MB of On-Chip L3 RAM
Level 3 (L3) and Level 4 (L4) Interconnects
Two DDR2/DDR3/DDR3L Memory Interface (EMIF) Modules
- Supports up to DDR2-800 and DDR3-1333
- Up to 2GB Supported per EMIF
Dual Arm® Cortex®-M4 Image Processing Units (IPU)
Vision AccelerationPac
- Up to Two Embedded Vision Engines (EVEs)
Imaging Subsystem (ISS)
- Image Signal Processor (ISP)
- Wide Dynamic Range and Lens Distortion Correction (WDR and Mesh LDC)
- One Camera Adaptation Layer (CAL_B)
IVA-HD Subsystem
Display Subsystem
- Display Controller with DMA Engine and up to Three Pipelines
- HDMI™ Encoder: HDMI 1.4a and DVI 1.0 Compliant
2D-Graphics Accelerator (BB2D) Subsystem
- Vivante^® GC320 Core
Video Processing Engine (VPE)
Dual-Core PowerVR^® SGX544 3D GPU
Two Video Input Port (VIP) Modules
- Support for up to Eight Multiplexed Input Ports
General-Purpose Memory Controller (GPMC)
Enhanced Direct Memory Access (EDMA) Controller
2-Port Gigabit Ethernet (GMAC)
Up to Two Controller Area Network (DCAN) Modules
- CAN 2.0B Protocol
Modular Controller Area Network (MCAN) Module
- CAN 2.0B Protocol with Available FD (Flexible Data Rate) Functionality
PCI Express^® 3.0 Port with Integrated PHY
- One 2-Lane Gen2-Compliant Port
- or Two 1-Lane Gen2-Compliant Ports
Sixteen 32-Bit General-Purpose Timers
32-Bit MPU Watchdog Timer
Ten Configurable UART/IrDA/CIR Modules
Four Multichannel Serial Peripheral Interfaces (McSPI)
Quad SPI Interface
Five Inter-Integrated Circuit (I²C) Ports
SATA Interface
Eight Multichannel Audio Serial Port (McASP) Modules
SuperSpeed USB 3.0 Dual-Role Device
Three High-Speed USB 2.0 Dual-Role Devices
Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD^®/SDIO)
Up to 247 General-Purpose I/O (GPIO) Pins
Real-Time Clock Subsystem (RTCSS)
Device Security Features
- Hardware Crypto Accelerators and DMA
- Firewalls
- JTAG^® Lock
- Secure Keys
- Secure ROM and Boot
- Customer Programmable Keys and OTP Data
Power, Reset, and Clock Management
On-Chip Debug With CTools Technology
Automotive AEC-Q100 Qualified
28-nm CMOS Technology
23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABZ)

TI’s new TDA2Px System-on-Chip (SoC) is a highly optimized and scalable family of devices designed to meet the requirements of leading Advanced Driver Assistance Systems (ADAS). The TDA2Px family enables broad ADAS applications in automobiles by integrating an optimal mix of performance, low power and ADAS vision analytics processing that aims to facilitate a more autonomous and collision-free driving experience.

The TDA2Px SoC enables sophisticated embedded vision technology in automobiles by broadest range of ADAS applications including front camera, park assist, surround view and sensor fusion on a single architecture.

The TDA2Px SoC incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed and floating-point TMS320C66x digital signal processor (DSP) generation cores, Vision AccelerationPac, Arm Cortex-A15 MPCore™ and dual-Cortex-M4 processors. The integration of a video accelerator for decoding multiple video streams over an Ethernet AVB network, along with graphics accelerators for rendering virtual views, enable a 3D viewing experience. And the TDA2Px SoC also integrates a host of peripherals including multi-camera interfaces (both parallel and serial) for LVDS-based surround view systems, displays, CAN and GigB Ethernet AVB.

The Vision AccelerationPac for this family of products includes multiple embedded vision engines (EVEs) offloading the vision analytics functionality from the application processor while also reducing the power footprint. The Vision AccelerationPac is optimized for vision processing with a 32-bit RISC core for efficient program execution and a vector coprocessor for specialized vision processing.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a debugging interface for visibility into source code execution.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The TDA2Px ADAS processor is qualified according to the AEC-Q100 standard.

TI’s new TDA2Px System-on-Chip (SoC) is a highly optimized and scalable family of devices designed to meet the requirements of leading Advanced Driver Assistance Systems (ADAS). The TDA2Px family enables broad ADAS applications in automobiles by integrating an optimal mix of performance, low power and ADAS vision analytics processing that aims to facilitate a more autonomous and collision-free driving experience.

The TDA2Px SoC enables sophisticated embedded vision technology in automobiles by broadest range of ADAS applications including front camera, park assist, surround view and sensor fusion on a single architecture.

The TDA2Px SoC incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed and floating-point TMS320C66x digital signal processor (DSP) generation cores, Vision AccelerationPac, Arm Cortex-A15 MPCore and dual-Cortex-M4 processors. The integration of a video accelerator for decoding multiple video streams over an Ethernet AVB network, along with graphics accelerators for rendering virtual views, enable a 3D viewing experience. And the TDA2Px SoC also integrates a host of peripherals including multi-camera interfaces (both parallel and serial) for LVDS-based surround view systems, displays, CAN and GigB Ethernet AVB.