計算工具
BLDC-MAX-QG-MOSFET-CALCULATOR — Calculate the maximum QG MOSFET for your motor driver
Calculate the maximum QG MOSFET that can be driven based on the PWM switching frequency, algorithm type, and additional external capacitance.
DRV8340-Q1
- AEC-Q100 qualified for automotive applications
- Temperature grade 1: –40°C ≤ TA ≤ 125°C
- Three independent half-bridge gate driver
- Dedicated source (SHx) and drain (DLx) pins to support independent MOSFET control
- Drives 3 high-side and 3 low-side N-channel MOSFETs (NMOS)
- Smart gate drive architecture
- Adjustable slew rate control
- 1.5-mA to 1-A peak source current
- 3-mA to 2-A peak sink current
- Charge-pump of gate driver for 100% Duty Cycle
- SPI (S) and hardware (H) interface available
- 6x, 3x, 1x, and independent PWM modes
- Supports 3.3-V, and 5-V logic inputs
- Charge pump output can be used to drive the reverse supply protection MOSFET
- Linear voltage regulator, 3.3 V, 30 mA
- Integrated protection features
- VM undervoltage lockout (UVLO)
- Charge pump undervoltage (CPUV)
- Short to battery (SHT_BAT)
- Short to ground (SHT_GND)
- MOSFET overcurrent protection (OCP)
- Gate driver fault (GDF)
- Thermal warning and shutdown (OTW/OTSD)
- Fault condition indicator (nFAULT)
The DRV8340-Q1 device is an integrated gate driver for three-phase applications. The device provides three half-bridge gate drivers, each capable of driving high-side and low-side N-channel power MOSFETs. The dedicated Source and Drain pins enable the independent MOSFET control for solenoid application. The DRV8340-Q1 generates the correct gate drive voltages using an integrated charge pump sufficient for the high-side MOSFETs and a linear regulator for the low-side MOSFETs. The Smart Gate Drive architecture supports peak gate drive currents up to 1-A source and 2-A. The DRV8340-Q1 can operate from a single power supply and supports a wide input supply range of 5.5 to 60 V for the gate driver.
The 6x, 3x, 1x, and independent input PWM modes allow for simple interfacing to controller circuits. The configuration settings for the gate driver and device are highly configurable through the SPI or hardware (H/W) interface.
A low-power sleep mode is provided to achieve low quiescent current. Internal protection functions are provided for undervoltage lockout, charge pump fault, MOSFET overcurrent, MOSFET short circuit, phase-node short to supply and ground, gate driver fault, and overtemperature. Fault conditions are indicated on the nFAULT pin with details through the device registers for the SPI device variant.
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檢視所有 3 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DRV8340-Q1 12-V / 24-V Automotive Gate Driver Unit (GDU) with Independent Half Bridge Control datasheet | PDF | HTML | 2017年 3月 9日 |
| Application note | System Design Considerations for High-Power Motor Driver Applications | PDF | HTML | 2021年 6月 22日 | |
| Application note | Switched Reluctance Motor (SRM) Inverter Design With the DRV8343-Q1 | 2020年 1月 30日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
開發板
DRV8343H-Q1EVM — DRV8343H-Q1 車用三相馬達智慧閘極驅動器評估模組
The DRV8343H-Q1EVM evaluation module is a 6V to 60V, 20A, a highly configurable 3-phase brushless DC (BLDC) motor drive and control evaluation platform designed for 12-V to 24-V automotive systems based on the DRV8343H-Q1 automotive smart gate driver. The EVM has onboard reverse battery (...)
使用指南: PDF
開發板
DRV8343S-Q1EVM — DRV8343S-Q1 車用三相馬達智慧閘極驅動器評估模組
The DRV8343S-Q1EVM evaluation module is a 6V to 60V, 20A, a highly configurable 3-phase brushless DC (BLDC) motor drive and control evaluation platform designed for 12-V to 24-V automotive systems based on the DRV8343S-Q1 automotive smart gate driver. The EVM has onboard reverse battery (...)
使用指南: PDF
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| HTQFP (PHP) | 48 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點