產品詳細資料

Rating Automotive Architecture Gate driver Control interface 1xPWM, 3xPWM, 6xPWM Gate drive (A) 1 Vs (min) (V) 5.5 Vs ABS (max) (V) 65 Features Current sense Amplifier, Hardware Management I/F, Independent FET Control, SPI/I2C, Smart Gate Drive Operating temperature range (°C) -40 to 125
Rating Automotive Architecture Gate driver Control interface 1xPWM, 3xPWM, 6xPWM Gate drive (A) 1 Vs (min) (V) 5.5 Vs ABS (max) (V) 65 Features Current sense Amplifier, Hardware Management I/F, Independent FET Control, SPI/I2C, Smart Gate Drive Operating temperature range (°C) -40 to 125
HTQFP (PHP) 48 81 mm² 9 x 9
  • AEC-Q100 qualified for automotive applications
    • Temperature grade 1: –40°C ≤ TA ≤ 125°C
  • Three independent half-bridge gate driver
    • Dedicated source (SHx) and drain (DLx) pins to support independent MOSFET control
    • Drives 3 high-side and 3 low-side N-channel MOSFETs (NMOS)
  • Smart gate drive architecture
    • Adjustable slew rate control
    • 1.5-mA to 1-A peak source current
    • 3-mA to 2-A peak sink current
  • Charge-pump of gate driver for 100% Duty Cycle
  • 3 Integrated current sense amplifiers (CSAs)
    • Adjustable gain (5, 10, 20, 40 V/V)
    • Bidirectional or unidirectional support
  • SPI (S) and hardware (H) interface available
  • 6x, 3x, 1x, and independent PWM modes
  • Supports 3.3-V, and 5-V logic inputs
  • Charge pump output can be used to drive the reverse supply protection MOSFET
  • Linear voltage regulator, 3.3 V, 30 mA
  • Integrated protection features
    • VM undervoltage lockout (UVLO)
    • Charge pump undervoltage (CPUV)
    • Short to battery (SHT_BAT)
    • Short to ground (SHT_GND)
    • MOSFET overcurrent protection (OCP)
    • Gate driver fault (GDF)
    • Thermal warning and shutdown (OTW/OTSD)
    • Fault condition indicator (nFAULT)
  • AEC-Q100 qualified for automotive applications
    • Temperature grade 1: –40°C ≤ TA ≤ 125°C
  • Three independent half-bridge gate driver
    • Dedicated source (SHx) and drain (DLx) pins to support independent MOSFET control
    • Drives 3 high-side and 3 low-side N-channel MOSFETs (NMOS)
  • Smart gate drive architecture
    • Adjustable slew rate control
    • 1.5-mA to 1-A peak source current
    • 3-mA to 2-A peak sink current
  • Charge-pump of gate driver for 100% Duty Cycle
  • 3 Integrated current sense amplifiers (CSAs)
    • Adjustable gain (5, 10, 20, 40 V/V)
    • Bidirectional or unidirectional support
  • SPI (S) and hardware (H) interface available
  • 6x, 3x, 1x, and independent PWM modes
  • Supports 3.3-V, and 5-V logic inputs
  • Charge pump output can be used to drive the reverse supply protection MOSFET
  • Linear voltage regulator, 3.3 V, 30 mA
  • Integrated protection features
    • VM undervoltage lockout (UVLO)
    • Charge pump undervoltage (CPUV)
    • Short to battery (SHT_BAT)
    • Short to ground (SHT_GND)
    • MOSFET overcurrent protection (OCP)
    • Gate driver fault (GDF)
    • Thermal warning and shutdown (OTW/OTSD)
    • Fault condition indicator (nFAULT)

The DRV8343-Q1 device is an integrated gate driver for three-phase applications. The device provides three half-bridge gate drivers, each capable of driving high-side and low-side N-channel power MOSFETs. The dedicated Source and Drain pins enable the independent MOSFET control for solenoid application. The DRV8343-Q1 generates the correct gate drive voltages using an integrated charge pump sufficient for the high-side MOSFETs and a linear regulator for the low-side MOSFETs. The Smart Gate Drive architecture supports peak gate drive currents up to 1-A source and 2-A. The DRV8343-Q1 can operate from a single power supply and supports a wide input supply range of 5.5 to 60 V for the gate driver.

The 6x, 3x, 1x, and independent input PWM modes allow for simple interfacing to controller circuits. The configuration settings for the gate driver and device are highly configurable through the SPI or hardware (H/W) interface. The DRV8343-Q1 device integrates three low-side current sense amplifiers that allow bidirectional current sensing on all three phases of the drive stage.

A low-power sleep mode is provided to achieve low quiescent current. Internal protection functions are provided for undervoltage lockout, charge pump fault, MOSFET overcurrent, MOSFET short circuit, phase-node short to supply and ground, gate driver fault, and overtemperature. Fault conditions are indicated on the nFAULT pin with details through the device registers for the SPI device variant.

The DRV8343-Q1 device is an integrated gate driver for three-phase applications. The device provides three half-bridge gate drivers, each capable of driving high-side and low-side N-channel power MOSFETs. The dedicated Source and Drain pins enable the independent MOSFET control for solenoid application. The DRV8343-Q1 generates the correct gate drive voltages using an integrated charge pump sufficient for the high-side MOSFETs and a linear regulator for the low-side MOSFETs. The Smart Gate Drive architecture supports peak gate drive currents up to 1-A source and 2-A. The DRV8343-Q1 can operate from a single power supply and supports a wide input supply range of 5.5 to 60 V for the gate driver.

The 6x, 3x, 1x, and independent input PWM modes allow for simple interfacing to controller circuits. The configuration settings for the gate driver and device are highly configurable through the SPI or hardware (H/W) interface. The DRV8343-Q1 device integrates three low-side current sense amplifiers that allow bidirectional current sensing on all three phases of the drive stage.

A low-power sleep mode is provided to achieve low quiescent current. Internal protection functions are provided for undervoltage lockout, charge pump fault, MOSFET overcurrent, MOSFET short circuit, phase-node short to supply and ground, gate driver fault, and overtemperature. Fault conditions are indicated on the nFAULT pin with details through the device registers for the SPI device variant.

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類型 標題 日期
* Data sheet DRV8343-Q1 12-V / 24-V Automotive Gate Driver Unit (GDU) with Independent Half Bridge Control and Three Integrated Current Sense Amplifiers datasheet (Rev. A) PDF | HTML 2019年 4月 9日
Application note Using DRV to Drive Solenoids (Rev. A) PDF | HTML 2022年 4月 24日
Application note Best Practices for Board Layout of Motor Drivers (Rev. B) PDF | HTML 2021年 10月 14日
Application note Hardware Design Considerations for an Electric Bicycle using BLDC Motor (Rev. B) 2021年 6月 23日
Application note System Design Considerations for High-Power Motor Driver Applications PDF | HTML 2021年 6月 22日
Technical article A basic brushless gate driver design – part 3: integrated vs. discrete half bridge PDF | HTML 2020年 12月 16日
Technical article How analog integration simplifies automotive body motor controller designs PDF | HTML 2020年 10月 23日
Technical article How to efficiently drive 12-V and 24-V engine loads in automotive systems PDF | HTML 2020年 7月 9日
Application note Switched Reluctance Motor (SRM) Inverter Design With the DRV8343-Q1 2020年 1月 30日
EVM User's guide DRV8343H-Q1EVM and DRV8343S-Q1EVM User's Guide (Rev. B) 2019年 4月 18日
Application note Protecting Automotive Motor Drive Systems from Reverse Polarity Conditions (Rev. A) 2019年 2月 19日
User guide DRV8343x-Q1EVM GUI User's Guide 2018年 1月 29日
EVM User's guide DRV8343x-Q1EVM Independent Mode User's Guide 2018年 1月 29日
EVM User's guide DRV8343x-Q1EVM Sensored Software User's Guide 2018年 1月 29日
EVM User's guide DRV8343x-Q1EVM Sensorless Software User's Guide 2018年 1月 29日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

DRV8343H-Q1EVM — DRV8343H-Q1 車用三相馬達智慧閘極驅動器評估模組

The DRV8343H-Q1EVM evaluation module is a 6V to 60V, 20A, a highly configurable 3-phase brushless DC (BLDC) motor drive and control evaluation platform designed for 12-V to 24-V automotive systems based on the DRV8343H-Q1 automotive smart gate driver.  The EVM has onboard reverse battery (...)
使用指南: PDF
TI.com 無法提供
開發板

DRV8343S-Q1EVM — DRV8343S-Q1 車用三相馬達智慧閘極驅動器評估模組

The DRV8343S-Q1EVM evaluation module is a 6V to 60V, 20A, a highly configurable 3-phase brushless DC (BLDC) motor drive and control evaluation platform designed for 12-V to 24-V automotive systems based on the DRV8343S-Q1 automotive smart gate driver.  The EVM has onboard reverse battery (...)
使用指南: PDF
TI.com 無法提供
模擬型號

DRV834XQ1 PSPICE Model

SLVMD44.ZIP (246 KB) - PSpice Model
計算工具

BLDC-MAX-QG-MOSFET-CALCULATOR Calculate the maximum QG MOSFET for your motor driver

Calculate the maximum QG MOSFET that can be driven based on the PWM switching frequency, algorithm type, and additional external capacitance.
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支援產品和硬體

產品
BLDC 驅動器
DRV8320 65 V 最大 3 相智慧型閘極驅動器 DRV8320R 具降壓穩壓器的 65-V 最大 3 相智慧型閘極驅動器 DRV8323 具電流分流放大器的 65-V 最大 3 相智慧型閘極驅動器 DRV8323R 具降壓穩壓器和電流分流放大器的 65V 最大三相智慧型閘極驅動器 DRV8329 具有單電流感測放大器的 60V 3 相閘極驅動器 DRV8329-Q1 具有單電流感測放大器的車用 60V 3 相閘極驅動器 DRV8334 具有準確電流感測功能的 60-V 1000-mA 至 2000-mA 3 相閘極驅動器 DRV8340-Q1 車用 12V 至 24V 電池 3 相智慧型閘極驅動器 DRV8343-Q1 具有電流分流放大器的車用 12V 至 24V 電池 3 相智慧型閘極驅動器 DRV8350 102V 最大三相智慧型閘極驅動器 DRV8350F 102-V 最大 3 相位功能安全品質管理智慧型閘極驅動器 DRV8350R 具降壓穩壓器的 102-V 最大 3 相智慧型閘極驅動器 DRV8353 具電流分流放大器的 102V 最大 3 相智慧型閘極驅動器 DRV8353F 具有 3x CSA 的 102-V 最大 3 相位功能安全品質管理智慧型閘極驅動器 DRV8353M 具有電流分流放大器和廣泛溫度的 102-V 最大 3 相智慧型閘極驅動器 DRV8353R 具降壓穩壓器和電流分流放大器的 102-V 最大 3 相智慧型閘極驅動器
參考設計

TIDA-060030 — 車用 12-V 至 24-V 引擎負載介面參考設計

This reference design is a 3-phase 1/2 H-Bridge Motor Drive solution with independent FET capability that interfaces with solenoid loads found in Gasoline and Diesel Engine Platforms such as automotive solenoids, bidirectional Brushed- or Brushless-DC motors, unidirectional Brushed-DC motors, and (...)
Design guide: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
HTQFP (PHP) 48 Ultra Librarian

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  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊:
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