DS25BR120
- DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation
- Four Levels of Transmit Pre-Emphasis Drive Lossy Backplanes and Cables
- On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space
- 7 kV ESD on LVDS I/O pins Protects Adjoining Components
- Small 3 mm x 3 mm 8-WSON Space Saving Package
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The DS25BR120 is a single channel 3.125 Gbps LVDS buffer optimized for high-speed signal transmission over lossy FR-4 printed circuit board backplanes and balanced metallic cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity.
The DS25BR120 features four levels of pre-emphasis (PE) for use as an optimized driver device. Other LVDS devices with similar IO characteristics include the following products. The DS25BR110 features four levels of equalization for use as an optimized receiver device, while the DS25BR100 features both pre-emphasis and equalization for use as an optimized repeater device. The DS25BR150 is a buffer/repeater with the lowest power consumption and does not feature transmit pre-emphasis nor receive equalization.
Wide input common mode range allows the receiver to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires minimal space on the board while the flow-through pinout allows easy board layout. The differential inputs and outputs are internally terminated with a 100Ω resistor to lower device input and output return losses, reduce component count and further minimize board space.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DS25BR120 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis datasheet (Rev. E) | 2013年 4月 14日 | |
| Application note | Applications of Low-Voltage Differential Signaling (LVDS) in LED Walls | 2020年 10月 29日 | ||
| Application note | Applications of Low-Voltage Differential Signaling (LVDS) in Ultrasound Scanners | 2019年 6月 29日 | ||
| Application note | LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A) | 2013年 4月 29日 | ||
| Application note | AN-1957 LVDS Signal Conditioners Reduce Data-Dependent Jitter (Rev. A) | 2013年 4月 26日 | ||
| User guide | 3.125 Gbps LVDS Buffers with Pre-emphasis and Equalization User Guide | 2012年 1月 25日 |
設計與開發
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DS25BR100EVK — 具有傳輸預強調和接收等化的 3.125 Gbps LVDS 單通道緩衝器系列
The DS25BR100EVK is an evaluation kit designed for demonstrating performance of the 3.125 Gbps LVDS Single Channel Buffers with Transmit Pre-Emphasis (PE) and Receive Equalization (EQ) family (DS25BR100, DS25BR110 and DS25BR120). The evaluation kit provides all three devices on a single board and (...)
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| WSON (NGQ) | 8 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。