DS90C031QML
- Radiation guaranteed 100 krad(Si)
- High impedance LVDS outputs with power-off
- ±350 mV differential signaling
- Low power dissipation
- Low differential skew
- Low propagation delay
- Pin compatible with DS26C31
- Compatible with IEEE 1596.3 SCI LVDS standard
- Compatible with proposed TIA LVDS standard
- Fail safe logic for floating inputs
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The DS90C031 is a quad CMOS differential line driver designed for applications requiring ultra low power dissipation and high data rates.
The DS90C031 accepts TTL/CMOS input levels and translates them to low voltage (350 mV) differential output signals. In addition the driver supports a TRI-STATE function that may be used to disable the output stage, thus dropping the device to a low idle power state of 11 mW typical.
In addition, the DS90C031 provides power-off high impedance LVDS outputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present. The DS90C031 and companion line receiver (DS90C032) provide a new alternative to high power psuedo-ECL devices for high speed point-to-point interface applications.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DS90C031QML LVDS Quad CMOS Differential Line Driver datasheet (Rev. B) | 2013年 3月 4日 | |
| * | SMD | DS90C031QML SMD 5962-95833 | 2016年 6月 21日 | |
| * | Radiation & reliability report | DS90C031xRQMLV SEE Report | 2012年 5月 9日 | |
| * | Radiation & reliability report | DS90C031xRQMLV TID Report | 2012年 5月 9日 | |
| Application brief | How Far, How Fast Can You Operate LVDS Drivers and Receivers? | 2018年 8月 3日 | ||
| Application brief | How to Terminate LVDS Connections with DC and AC Coupling | 2018年 5月 16日 | ||
| More literature | Die D/S DS90C031 MDR Lvds Quad Cmos Differential Line Driver | 2012年 9月 7日 | ||
| Application note | AN-1110 LVDS Quad Dynamic I CC vs Frequency | 2004年 5月 15日 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| LCCC (NAJ) | 20 | Ultra Librarian |
訂購與品質
- RoHS
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