DS90C032B
- >155.5 Mbps (77.7 MHz) Switching Rates
- Accepts Small Swing (350 mV) Differential Signal Levels
- High Impedance LVDS Inputs with Power Down
- Ultra Low Power Dissipation
- 600 ps Maximum Differential Skew (5V, 25°C)
- 6.0 ns Maximum Propagation Delay
- Industrial Operating Temperature Range
- Available in Surface Mount Packaging (SOIC)
- Pin Compatible with DS26C32A, MB570 (PECL) and 41LF (PECL)
- Supports OPEN and Terminated Input Failsafe
- Conforms to ANSI/TIA/EIA-644 LVDS Standard
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The DS90C032B is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The device supports data rates in excess of 155.5 Mbps (77.7 MHz) and uses Low Voltage Differential Signaling (LVDS) technology.
The DS90C032B accepts low voltage (350 mV) differential input signals and translates them to CMOS (TTL compatible) output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports OPEN Failsafe and terminated (100Ω) input Failsafe with the addition of external failsafe biasing. Receiver output will be HIGH for both Failsafe conditions.
The DS90C032B provides power-off high impedance LVDS inputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present.
The DS90C032B and companion line driver (DS90C031B) provide a new alternative to high power pseudo-ECL devices for high-speed point-to-point interface applications.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | DS90C032B LVDS Quad CMOS Differential Line Receiver datasheet (Rev. C) | 2013年 4月 12日 | |
Application brief | How Far, How Fast Can You Operate LVDS Drivers and Receivers? | 2018年 8月 3日 | ||
Application brief | How to Terminate LVDS Connections with DC and AC Coupling | 2018年 5月 16日 | ||
Application note | AN-1110 LVDS Quad Dynamic I CC vs Frequency | 2004年 5月 15日 | ||
Application note | An Overview of LVDS Technology | 1998年 10月 5日 |
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---|---|---|
SOIC (D) | 16 | Ultra Librarian |
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