DS90C032QML
- Single Event Latchup (SEL) Immune 120 MeV-cm2/mg
- High Impedance LVDS Inputs with Power-Off.
- Accepts Small Swing (330 mV) Differential Signal Levels
- Low Power Dissipation
- Low Differential Skew
- Low Chip to Chip Skew
- Pin Compatible with DS26C32A
- Compatible with IEEE 1596.3 SCI LVDS Standard
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The DS90C032 is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates.
The DS90C032 accepts low voltage differential input signals and translates them to CMOS (TTL compatible) output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports OPEN Failsafe and terminated (100Ω) input Failsafe with the addition of external failsafe biasing. Receiver output will be HIGH for both Failsafe conditions.
The DS90C032 provides power-off high impedance LVDS inputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present.
The DS90C032 and companion line driver (DS90C031) provide a new alternative to high power pseudo-ECL devices for high speed point-to-point interface applications.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DS90C032QML LVDS Quad CMOS Differential Line Receiver datasheet (Rev. D) | 2013年 4月 12日 | |
| * | SMD | DS90C032QML SMD 5962-95834 | 2016年 6月 21日 | |
| * | Radiation & reliability report | DS90C032xLQMLV SEE Report | 2012年 5月 9日 | |
| * | Radiation & reliability report | DS90C032xLQMLV TID Report | 2012年 5月 9日 | |
| Application brief | How Far, How Fast Can You Operate LVDS Drivers and Receivers? | 2018年 8月 3日 | ||
| Application brief | How to Terminate LVDS Connections with DC and AC Coupling | 2018年 5月 16日 | ||
| More literature | Die D/S DS90C032 MDR Lvds Quad Cmos Differential Line Receiver | 2012年 9月 7日 | ||
| Application note | AN-1110 LVDS Quad Dynamic I CC vs Frequency | 2004年 5月 15日 |
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|---|---|---|
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