DS90CR486
- Up to 6.384 Gbps Throughput
- 66MHz to 133MHz Input Clock Support
- Reduces Cable and Connector Size and Cost
- Cable Deskew Function
- DC Balance Reduces ISI Distortion
- For Point-to-Point Backplane or Cable Applications
- Low Power, 890 mW Typ at 133MHz
- Flow through Pinout for Easy PCB Design
- +3.3V Supply Voltage
- 100-pin TQFP Package
- Conforms to TIA/EIA-644-A-2001 LVDS Standard
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The DS90CR486 receiver converts eight Low Voltage Differential Signaling (LVDS) data streams back into 48 bits of LVCMOS/LVTTL data. Using a 133MHz clock, the data throughput is 6.384Gbit/s (798Mbytes/s).
The multiplexing of data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 48-bit wide data and one clock, up to 98 conductors are required. With this Channel Link chipset as few as 19 conductors (8 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides an 80% reduction in interconnect width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form factor.
The DS90CR486 deserializer is improved over prior generations of Channel Link devices and offers higher bandwidth support and longer cable drive with three areas of enhancement. To increase bandwidth, the maximum clock rate is increased to 133 MHz and 8 serialized LVDS outputs are provided. Cable drive is enhanced with a user selectable pre-emphasis (on DS90CR485) feature that provides additional output current during transitions to counteract cable loading effects. Optional DC balancing on a cycle-to-cycle basis, is also provided to reduce ISI (Inter-Symbol Interference). With pre-emphasis and DC balancing, a low distortion eye-pattern is provided at the receiver end of the cable. A cable deskew capability has been added to deskew long cables of pair-to-pair skew. These three enhancements allow long cables to be driven.
The DS90CR486 is intended to be used with the DS90CR485 Channel Link Serializer. It is also backward compatible with serializers DS90CR481 and DS90CR483. The DS90CR486 is footprint compatible with the DS90CR484.
The chipset is an ideal solution to solve EMI and interconnect size problems for high-throughput point-to-point applications.
For more details, please refer to the section of this datasheet.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DS90CR486 133MHz 48-Bit Channel Link Deserializer (6.384 Gbps) datasheet (Rev. C) | 2013年 3月 5日 | |
| Application note | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 2018年 11月 9日 | ||
| EVM User's guide | 48-bit Channel Link Serializer Deserializer Evaluation Board 133MHz | 2012年 1月 26日 | ||
| Design guide | Channel Link I Design Guide | 2007年 3月 29日 | ||
| Application note | Multi-Drop Channel-Link Operation | 2004年 10月 4日 | ||
| White paper | The Many Flavors of LVDS | 2002年 2月 1日 | ||
| Application note | CHANNEL LINK Moving and Shaping Information In Point-To-Point Applications | 1998年 10月 5日 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| QFP (NEZ) | 100 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
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