DS90LV032AQML
- Low chip to chip skew
- Low differential skew
- High impedance LVDS inputs with power-off
- Low power dissipation
- Accepts small swing (330 mV) differential signal levels.
- Compatible with ANSI/TIA/EIA-644
- Operating temperature range (-55°C to +85°C)
- Pin compatible with DS90C032A and DS26C32A.
- Typical Rise/Fall time is 350pS.
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The DS90LV032A is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates.
The DS90LV032A accepts low voltage (350 mV typical) differential input signals and translates them to 3V CMOS output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs.
The DS90LV032A and companion LVDS line driver (eg. DS90LV031A) provide a new alternative to high power PECL/ECL devices for high speed point-to-point interface applications.
In addition, the DS90LV032A provides power-off high impedance LVDS inputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DS90LV032AQML 3V LVDS Quad CMOS Differential Line Receiver datasheet (Rev. A) | 2013年 4月 16日 | |
| * | SMD | DS90LV032AQML SMD 5962-98652 | 2016年 6月 21日 | |
| Application brief | How Far, How Fast Can You Operate LVDS Drivers and Receivers? | 2018年 8月 3日 | ||
| Application brief | How to Terminate LVDS Connections with DC and AC Coupling | 2018年 5月 16日 | ||
| More literature | Die D/S DS90LV032 MDS 3V LVDS Quad Cmos Differential Line Receiver | 2012年 9月 7日 |
設計與開發
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DS90LV047-48AEVM — DS90LV047-48AEVM 評估模組
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| CFP (NAD) | 16 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。