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DS92LV3222

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20-50 MHz 32 位元 Channel Link II 解串器

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DS92LV3222

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Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
TQFP (PAG) 64 144 mm² 12 x 12
  • Wide Operating Range Embedded Clock SER/DES
    • Up to 32-bit Parallel LVCMOS Data
    • 20 to 50 MHz Parallel Clock
    • Up to 1.6 Gbps Application Data Paylod
  • Simplified Clocking Architecture
    • No Separate Serial Clock Line
    • No Reference Clock Required
    • Receiver Locks to Random Data
  • On-chip Signal Conditioning for Robust Serial Connectivity
    • Transmit Pre-Emphasis
    • Data Randomization
    • DC-Balance Encoding
    • Receive Channel Deskew
    • Supports up to 10m CAT-5 at 1.6Gbps
  • Integrated LVDS Terminations
  • Built-in AT-SPEED BIST for End-To-End System Testing
  • AC-Coupled Interconnect for Isolation and Fault Protection
  • > 4KV HBM ESD Protection
  • Space-Saving 64-pin TQFP Package
  • Full Industrial Temperature Range: -40° to +85°C

All trademarks are the property of their respective owners.

  • Wide Operating Range Embedded Clock SER/DES
    • Up to 32-bit Parallel LVCMOS Data
    • 20 to 50 MHz Parallel Clock
    • Up to 1.6 Gbps Application Data Paylod
  • Simplified Clocking Architecture
    • No Separate Serial Clock Line
    • No Reference Clock Required
    • Receiver Locks to Random Data
  • On-chip Signal Conditioning for Robust Serial Connectivity
    • Transmit Pre-Emphasis
    • Data Randomization
    • DC-Balance Encoding
    • Receive Channel Deskew
    • Supports up to 10m CAT-5 at 1.6Gbps
  • Integrated LVDS Terminations
  • Built-in AT-SPEED BIST for End-To-End System Testing
  • AC-Coupled Interconnect for Isolation and Fault Protection
  • > 4KV HBM ESD Protection
  • Space-Saving 64-pin TQFP Package
  • Full Industrial Temperature Range: -40° to +85°C

All trademarks are the property of their respective owners.

The DS92LV3221 (SER) serializes a 32-bit data bus into 2 embedded clock LVDS serial channels for a data payload rate up to 1.6 Gbps over cables such as CATx, or backplanes FR-4 traces. The companion DS92LV3222 (DES) deserializes the 2 LVDS serial data channels, de-skews channel-to-channel delay variations and converts the LVDS data stream back into a 32-bit LVCMOS parallel data bus.

On-chip data Randomization/Scrambling and DC balance encoding and selectable serializer Pre-emphasis ensure a robust, low-EMI transmission over longer, lossy cables and backplanes. The Deserializer automatically locks to incoming data without an external reference clock or special sync patterns, providing an easy “plug-and-lock” operation.

By embedding the clock in the data payload and including signal conditioning functions, the Channel-Link II SerDes devices reduce trace count, eliminate skew issues, simplify design effort and lower cable/connector cost for a wide variety of video, control and imaging applications. A built-in AT-SPEED BIST feature validates link integrity and may be used for system diagnostics.

The DS92LV3221 (SER) serializes a 32-bit data bus into 2 embedded clock LVDS serial channels for a data payload rate up to 1.6 Gbps over cables such as CATx, or backplanes FR-4 traces. The companion DS92LV3222 (DES) deserializes the 2 LVDS serial data channels, de-skews channel-to-channel delay variations and converts the LVDS data stream back into a 32-bit LVCMOS parallel data bus.

On-chip data Randomization/Scrambling and DC balance encoding and selectable serializer Pre-emphasis ensure a robust, low-EMI transmission over longer, lossy cables and backplanes. The Deserializer automatically locks to incoming data without an external reference clock or special sync patterns, providing an easy “plug-and-lock” operation.

By embedding the clock in the data payload and including signal conditioning functions, the Channel-Link II SerDes devices reduce trace count, eliminate skew issues, simplify design effort and lower cable/connector cost for a wide variety of video, control and imaging applications. A built-in AT-SPEED BIST feature validates link integrity and may be used for system diagnostics.
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* Data sheet DS92LV3221/3222 20-50 MHz 32-Bit Channel Link II Serializer / Deserializer datasheet (Rev. C) 2013年 4月 16日

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  • 進行中持續性的可靠性監測
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