首頁 介面 其它介面
首頁
介面
其它介面

DS99R103

最後一次購買

3-MHz 至 40MHz 直流平衡 24 位元 LVDS 串聯器，適用 -40C 至 85C

立即訂購
產品規格表

DS99R103

最後一次購買
產品規格表 立即訂購

產品詳細資料

Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
TQFP (PFB) 48 81 mm² 9 x 9 WQFN (NJU) 48 49 mm² 7 x 7
  • 3 MHz–40 MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data Transmissions
  • Capable to Drive Shielded Twisted-Pair Cable
  • User Selectable Clock Edge for Parallel Data on both Transmitter and Receiver
  • Internal DC Balancing Encode/Decode – Supports AC-Coupling Interface with no External Coding Required
  • Individual Power-Down Controls for both Transmitter and Receiver
  • Embedded Clock CDR (Clock and Data Recovery) on Receiver and no External Source of Reference Clock Needed
  • All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications
  • LOCK Output Flag to Ensure Data Integrity at Receiver Side
  • Balanced TSETUP/THOLD Between RCLK and RDATA on Receiver Side
  • PTO (Progressive Turn-On) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects
  • All LVCMOS inputs and control pins have internal pulldown
  • On-Chip Filters for PLLs on Transmitter and Receiver
  • Integrated 100Ω Input Termination on Receiver
  • 4 mA Receiver Output Drive
  • 48-Pin TQFP and 48-Pin WQFN Packages
  • Pure CMOS .35 μm Process
  • Power Supply Range 3.3V ± 10%
  • Temperature Range −40°C to +85°C
  • 8 kV HBM ESD Tolerance

All trademarks are the property of their respective owners.

  • 3 MHz–40 MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data Transmissions
  • Capable to Drive Shielded Twisted-Pair Cable
  • User Selectable Clock Edge for Parallel Data on both Transmitter and Receiver
  • Internal DC Balancing Encode/Decode – Supports AC-Coupling Interface with no External Coding Required
  • Individual Power-Down Controls for both Transmitter and Receiver
  • Embedded Clock CDR (Clock and Data Recovery) on Receiver and no External Source of Reference Clock Needed
  • All Codes RDL (Random Data Lock) to Support Live-Pluggable Applications
  • LOCK Output Flag to Ensure Data Integrity at Receiver Side
  • Balanced TSETUP/THOLD Between RCLK and RDATA on Receiver Side
  • PTO (Progressive Turn-On) LVCMOS Outputs to Reduce EMI and Minimize SSO Effects
  • All LVCMOS inputs and control pins have internal pulldown
  • On-Chip Filters for PLLs on Transmitter and Receiver
  • Integrated 100Ω Input Termination on Receiver
  • 4 mA Receiver Output Drive
  • 48-Pin TQFP and 48-Pin WQFN Packages
  • Pure CMOS .35 μm Process
  • Power Supply Range 3.3V ± 10%
  • Temperature Range −40°C to +85°C
  • 8 kV HBM ESD Tolerance

All trademarks are the property of their respective owners.

The DS99R103/DS99R104 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

The DS99R103/DS99R104 incorporates LVDS signaling on the high-speed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range EMI is further reduced.

In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.

The DS99R103/DS99R104 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

The DS99R103/DS99R104 incorporates LVDS signaling on the high-speed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range EMI is further reduced.

In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
filter 尋找其它 其它介面
下載

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 1
類型 標題 日期
* Data sheet DS99R103/DS99R104 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer datasheet (Rev. D) 2013年 4月 16日

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點