LP5900

現行

具啟用功能的 150-mA 低雜訊低 IQ 低壓降電壓穩壓器

產品詳細資料

Output options Fixed Output Iout (max) (A) 0.15 Vin (max) (V) 5.5 Vin (min) (V) 2.5 Vout (max) (V) 4.5 Vout (min) (V) 1.5 Fixed output options (V) 1.5, 1.575, 1.8, 1.9, 2, 2.1, 2.2, 2.3, 2.5, 2.6, 2.65, 2.7, 2.75, 2.8, 2.85, 3, 3.3, 4.5 Rating Catalog Noise (µVrms) 6.5 PSRR at 100 KHz (dB) 40 Iq (typ) (mA) 0.025 Thermal resistance θJA (°C/W) 80 Load capacitance (min) (µF) 0.47 Regulated outputs (#) 1 Features Enable Accuracy (%) 3 Dropout voltage (Vdo) (typ) (mV) 80 Operating temperature range (°C) -40 to 125
Output options Fixed Output Iout (max) (A) 0.15 Vin (max) (V) 5.5 Vin (min) (V) 2.5 Vout (max) (V) 4.5 Vout (min) (V) 1.5 Fixed output options (V) 1.5, 1.575, 1.8, 1.9, 2, 2.1, 2.2, 2.3, 2.5, 2.6, 2.65, 2.7, 2.75, 2.8, 2.85, 3, 3.3, 4.5 Rating Catalog Noise (µVrms) 6.5 PSRR at 100 KHz (dB) 40 Iq (typ) (mA) 0.025 Thermal resistance θJA (°C/W) 80 Load capacitance (min) (µF) 0.47 Regulated outputs (#) 1 Features Enable Accuracy (%) 3 Dropout voltage (Vdo) (typ) (mV) 80 Operating temperature range (°C) -40 to 125
DSBGA (YPF) 4 1.5625 mm² 1.25 x 1.25 DSBGA (YZR) 4 1.5625 mm² 1.25 x 1.25 WSON (NGF) 6 5.5 mm² 2.5 x 2.2
  • Input Voltage Range, 2.5 V to 5.5 V
  • Output Voltage Range, 1.5 V to 4.5 V
  • Stable with 0.47-μF Ceramic Input and Output Capacitors
  • No Noise Bypass Capacitor Required
  • Logic Controlled Enable
  • Thermal-Overload and Short-Circuit Protection
  • −40°C to 125°C Junction Temperature Range for Operation
  • Output Current, 150 mA
  • Low Output Voltage Noise, 6.5 μVRMS
  • PSRR, 75 dB at 1 kHz
  • Output Voltage Tolerance, ±2%
  • Virturally Zero IQ (Disabled), < 1 µA
  • Very Low IQ (Enabled), 25 μA
  • Start-up Time, 150 μs
  • Low Dropout, 80 mV Typ.
  • Input Voltage Range, 2.5 V to 5.5 V
  • Output Voltage Range, 1.5 V to 4.5 V
  • Stable with 0.47-μF Ceramic Input and Output Capacitors
  • No Noise Bypass Capacitor Required
  • Logic Controlled Enable
  • Thermal-Overload and Short-Circuit Protection
  • −40°C to 125°C Junction Temperature Range for Operation
  • Output Current, 150 mA
  • Low Output Voltage Noise, 6.5 μVRMS
  • PSRR, 75 dB at 1 kHz
  • Output Voltage Tolerance, ±2%
  • Virturally Zero IQ (Disabled), < 1 µA
  • Very Low IQ (Enabled), 25 μA
  • Start-up Time, 150 μs
  • Low Dropout, 80 mV Typ.

The LP5900 is an LDO capable of supplying 150-mA output current. Designed to meet the requirements of RF and analog circuits, the LP5900 device provides low noise, high PSRR, low quiescent current, and low line transient response figures. Using new innovative design techniques the LP5900 offers class-leading device noise performance without a noise bypass capacitor.

The device is designed to work with 0.47-μF input and output ceramic capacitors (no bypass capacitor required).

The device is available in a DSBGA (YZR) package and a WSON package; the device is also available in an extremely thin DSBGA (YPF) package. For all voltage and package options available today, see the Package Option Addendum (POA) at the end of this data sheet. For any other fixed output voltages from 1.5 V to 4.5 V in 25-mV steps and all other package options, contact your local TI Sales office.

For all available packages, see the orderable addendum at the end of the data sheet.

The LP5900 is an LDO capable of supplying 150-mA output current. Designed to meet the requirements of RF and analog circuits, the LP5900 device provides low noise, high PSRR, low quiescent current, and low line transient response figures. Using new innovative design techniques the LP5900 offers class-leading device noise performance without a noise bypass capacitor.

The device is designed to work with 0.47-μF input and output ceramic capacitors (no bypass capacitor required).

The device is available in a DSBGA (YZR) package and a WSON package; the device is also available in an extremely thin DSBGA (YPF) package. For all voltage and package options available today, see the Package Option Addendum (POA) at the end of this data sheet. For any other fixed output voltages from 1.5 V to 4.5 V in 25-mV steps and all other package options, contact your local TI Sales office.

For all available packages, see the orderable addendum at the end of the data sheet.

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類型 標題 日期
* Data sheet LP5900 150-mA Ultra-Low-Noise LDO for RF and Analog Circuits - Requires No Bypass Capacitor datasheet (Rev. R) PDF | HTML 2016年 6月 1日
Selection guide Power Management Guide 2018 (Rev. R) 2018年 6月 25日
Selection guide Low Dropout Regulators Quick Reference Guide (Rev. P) 2018年 3月 21日
Technical article How LDOs contribute to power efficiency PDF | HTML 2016年 5月 13日
EVM User's guide AN-1494 LP5900SD 6 Pin WSON Evaluation Board Information (Rev. B) 2013年 4月 30日
EVM User's guide AN-1396 LP5900 DSBGA Evaluation Board Information (Rev. C) 2013年 4月 29日
Application note AN-2145 Power Considerations for SDI Products (Rev. B) 2013年 4月 26日
Application note AN-2146 Power Design for SDI and Other Noise-Sensitive Devices (Rev. A) 2013年 4月 26日
Application note AN-1950 Silently Powering Low Noise Applications (Rev. A) 2013年 4月 22日
User guide High-IF Sub-sampling Receiver Subsystem User Guide 2012年 1月 27日
User guide SP16130CH4RB Low IF Receiver Reference Design User Guide 2012年 1月 27日
White paper Using Power to Improve Signal-Path Performance 2006年 8月 1日

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模擬型號

LP5900_1P5 PSpice Transient Model

SNVM636.ZIP (41 KB) - PSpice Model
模擬型號

LP5900_1P5 Unencrypted PSpice Transient Model

SNVMAA5.ZIP (1 KB) - PSpice Model
模擬型號

LP5900_2P8 PSpice Transient Model

SNVM635.ZIP (41 KB) - PSpice Model
模擬型號

LP5900_2P8 Unencrypted PSpice Transient Model

SNVMAA6.ZIP (1 KB) - PSpice Model
模擬型號

LP5900_3P0 Unencrypted PSpice Transient Model

SNVMAA4.ZIP (1 KB) - PSpice Model
模擬型號

LP5900_3P3 PSpice Transient Model

SNVM637.ZIP (42 KB) - PSpice Model
CAD/CAE 符號

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SNAC012.ZIP (3259 KB)
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
DSBGA (YPF) 4 Ultra Librarian
DSBGA (YZR) 4 Ultra Librarian
WSON (NGF) 6 Ultra Librarian

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