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LVDS、M-LVDS 和 PECL IC

SCAN90CP02

現行

具預強調和 IEEE 1149.6 功能的 1.5 Gbps 2x2 LVDS 交叉點開關

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產品規格表

SCAN90CP02

現行
產品規格表 立即訂購

產品詳細資料

Function Crosspoint Protocols BLVDS, CML, LVDS, LVPECL Number of transmitters 2 Number of receivers 2 Supply voltage (V) 3.3 Signaling rate (Mbps) 1500 Input signal CML, LVDS, LVPECL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Crosspoint Protocols BLVDS, CML, LVDS, LVPECL Number of transmitters 2 Number of receivers 2 Supply voltage (V) 3.3 Signaling rate (Mbps) 1500 Input signal CML, LVDS, LVPECL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
LQFP (NEY) 32 81 mm² 9 x 9 UQFN (NJD) 28 25 mm² 5 x 5
  • 1.5 Gbps per Channel
  • Low Power: 70 mA in Dual Repeater Mode @1.5 Gbps
  • Low Output Jitter
  • Configurable 0/25/50/100% Pre-Emphasis Drives Lossy Backplanes and Cables
  • Non-Blocking Architecture Allows 1:2 Splitter, 2:1 Mux, Crossover, and Dual Buffer Configurations
  • Flow-Through Pinout
  • LVDS/BLVDS/CML/LVPECL Inputs, LVDS Outputs
  • IEEE 1149.1 and 1149.6 Compliant
  • Single 3.3V Supply
  • Separate Control of Inputs and Outputs Allows for Power Savings
  • Industrial -40 to +85°C Temperature Range
  • 28-Lead UQFN Package, or 32-Lead LQFP Package

All trademarks are the property of their respective owners.

  • 1.5 Gbps per Channel
  • Low Power: 70 mA in Dual Repeater Mode @1.5 Gbps
  • Low Output Jitter
  • Configurable 0/25/50/100% Pre-Emphasis Drives Lossy Backplanes and Cables
  • Non-Blocking Architecture Allows 1:2 Splitter, 2:1 Mux, Crossover, and Dual Buffer Configurations
  • Flow-Through Pinout
  • LVDS/BLVDS/CML/LVPECL Inputs, LVDS Outputs
  • IEEE 1149.1 and 1149.6 Compliant
  • Single 3.3V Supply
  • Separate Control of Inputs and Outputs Allows for Power Savings
  • Industrial -40 to +85°C Temperature Range
  • 28-Lead UQFN Package, or 32-Lead LQFP Package

All trademarks are the property of their respective owners.

The SCAN90CP02 is a 1.5 Gbps 2 x 2 LVDS crosspoint switch. High speed data paths and flow-through pinout minimize internal device jitter, while configurable 0/25/50/100% pre-emphasis overcomes external ISI jitter effects of lossy backplanes and cables. The differential inputs interface to LVDS and Bus LVDS signals such as those on TI's 10-, 16-, and 18- bit Bus LVDS SerDes, as well as CML and LVPECL. The SCAN90CP02 can also be used with ASICs and FPGAs. The non-blocking crosspoint architecture is pin-configurable as a 1:2 clock or data splitter, 2:1 redundancy mux, crossover function, or dual buffer for signal booster and stub hider applications.

Integrated IEEE 1149.1 (JTAG) and 1149.6 circuitry supports testability of both single-ended LVTTL/CMOS and differential LVDS PCB interconnect. The 3.3V supply, CMOS process, and LVDS I/O ensure high performance at low power over the entire industrial -40 to +85°C temperature range.

The SCAN90CP02 is a 1.5 Gbps 2 x 2 LVDS crosspoint switch. High speed data paths and flow-through pinout minimize internal device jitter, while configurable 0/25/50/100% pre-emphasis overcomes external ISI jitter effects of lossy backplanes and cables. The differential inputs interface to LVDS and Bus LVDS signals such as those on TI's 10-, 16-, and 18- bit Bus LVDS SerDes, as well as CML and LVPECL. The SCAN90CP02 can also be used with ASICs and FPGAs. The non-blocking crosspoint architecture is pin-configurable as a 1:2 clock or data splitter, 2:1 redundancy mux, crossover function, or dual buffer for signal booster and stub hider applications.

Integrated IEEE 1149.1 (JTAG) and 1149.6 circuitry supports testability of both single-ended LVTTL/CMOS and differential LVDS PCB interconnect. The 3.3V supply, CMOS process, and LVDS I/O ensure high performance at low power over the entire industrial -40 to +85°C temperature range.
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類型 標題 日期
* Data sheet SCAN90CP02 1.5 Gbps 2x2 LVDS Crosspoint Switch w/Pre-Emphasis & IEEE 1149.6 datasheet (Rev. M) 2013年 4月 12日
Application note AN-1313 SCAN90CP02 Design for Test Features (Rev. C) 2013年 4月 26日
User guide SCAN90CP02 2x2 LVDS Cross-point Switch Evaluation Kit 2012年 2月 21日

設計與開發

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模擬型號

SCAN90CP02 BSDL Model

SNLM103.ZIP (218 KB) - BSDL Model
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模擬型號

SCAN90CP02 IBIS Model

SNLM004.ZIP (28 KB) - IBIS Model
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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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LQFP (NEY) 32 Ultra Librarian
UQFN (NJD) 28 Ultra Librarian
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