SN65ELT23
- Dual 5-V Differential PECL-to-TTL Buffer
- 24-mA TTL Ouputs
- Operating Range
- PECL VCC = 4.75 V to 5.25 V with GND = 0 V
- Support for Clock Frequencies of 250 MHz (TYP)
- 3.5-ns Typical Propagation Delay
- Output Default Low with Inputs Left Open or <1.3 V
- Internal Input 50-k
Pull-Down Resistor - Built-In Temperature Compensation
- Drop-In Compatible to the MC100ELT23
- APPLICATIONS
- Data and Clock Transmission Over Backplane
- Signaling Level Conversion for Clock or Data
The SN65ELT23 is a low power dual PECL-to-TTL translator device. The device includes circuitry to maintain a known logic low level when inputs are in an open condition. The SN65ELT23 is housed in an industry standard SOIC-8 package and is also available in an optional TSSOP-8 package.
技術文件
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檢視所有 2 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | 5-V Dual Differential PECL Buffer-to-TTL Translator datasheet | 2009年 6月 30日 | |
| Application note | AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) | 2007年 10月 17日 |
設計與開發
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模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (D) | 8 | Ultra Librarian |
| VSSOP (DGK) | 8 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。