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IO-Link 和數位 I/O

SN65HVD101

現行

適用裝置節點的 IO-Link PHY

立即訂購
產品規格表

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TIOL112 現行 具低殘餘電壓和整合式突波保護和的 IO-Link 裝置收發器 Device offers smaller package, integrated ESD, surge protection, Low residual voltage of 0.9 V (max), lower junction-to-ambient thermal resistance, slower driver slew rates to reduce overshoots
TIOL1123 現行 具有低殘餘電壓、整合式突波防護、3.3-V LDO 輸出的 IO-Link 裝置收發器 Device offers smaller package, integrated ESD, surge protection, Low residual voltage of 0.9 V (max), lower junction-to-ambient thermal resistance, slower driver slew rates to reduce overshoots and 3.3V LDO out
TIOL1125 現行 具有低殘餘電壓、整合式突波防護、5-V LDO 輸出的 IO-Link 裝置收發器 Device offers smaller package, integrated ESD, surge protection, Low residual voltage of 0.9 V (max), lower junction-to-ambient thermal resistance, slower driver slew rates to reduce overshoots and 5V LDO out

SN65HVD101

現行
產品規格表 立即訂購

產品詳細資料

Type IO-Link Supply voltage (V) 9 to 30 Current limit (max) (A) 0.4 LDO output range (V) 3.3 Features Adjustable IO, Configurable current limiter, Integrated LDO (3.3 V or 5 V), Remote wakeup, Reverse polarity protection, Thermal warning Operating temperature range (°C) -40 to 105
Type IO-Link Supply voltage (V) 9 to 30 Current limit (max) (A) 0.4 LDO output range (V) 3.3 Features Adjustable IO, Configurable current limiter, Integrated LDO (3.3 V or 5 V), Remote wakeup, Reverse polarity protection, Thermal warning Operating temperature range (°C) -40 to 105
VQFN (RGB) 20 14 mm² 4 x 3.5
  • Configurable CQ Output: Push-Pull, High-Side, or Low-Side for SIO Mode
  • Remote Wake-Up Indicator
  • Current Limit Indicator
  • Power-Good Indicator
  • Overtemperature Protection
  • Reverse Polarity Protection
  • Configurable Current Limits
  • 9-V to 36-V Supply Range
  • Tolerant to 50-V Peak Line Voltage
  • 3.3-V/5-V Configurable Integrated LDO (SN65HVD101 ONLY)
  • 20-pin QFN Package, 4 mm × 3.5 mm
  • Configurable CQ Output: Push-Pull, High-Side, or Low-Side for SIO Mode
  • Remote Wake-Up Indicator
  • Current Limit Indicator
  • Power-Good Indicator
  • Overtemperature Protection
  • Reverse Polarity Protection
  • Configurable Current Limits
  • 9-V to 36-V Supply Range
  • Tolerant to 50-V Peak Line Voltage
  • 3.3-V/5-V Configurable Integrated LDO (SN65HVD101 ONLY)
  • 20-pin QFN Package, 4 mm × 3.5 mm

The SN65HVD101 and ‘HVD102 IO-Link PHYs implement the IO-Link interface for industrial point-to-point communication. When the device is connected to an IO-Link master through a 3-wire interface, the master can initiate communication and exchange data with the remote node while the SN65HVD10X acts as a complete physical layer for the communication.

The IO-Link driver output (CQ) can be used in push-pull, high-side, or low-side configurations using the EN and TX input pins. The PHY receiver converts the 24-V IO-Link signal on the CQ pin to standard logic levels on the RX pin. A simple parallel interface is used to receive and transmit data and status information between the PHY and the local controller.

The SN65HVD101 and ’HVD102 implement protection features for overcurrent, overvoltage and overtemperature conditions. The IO-Link driver current limit can be set using an external resistor. If a short-circuit current fault occurs, the driver outputs are internally limited, and the PHY generates an error signal (SC). These devices also implement an overtemperature shutdown feature that protects the device from high-temperature faults.

The SN65HVD102 operates from a single external 3.3-V or 5-V local supply. The SN65HVD101 integrates a linear regulator that generates either 3.3 V or 5 V from the IO-Link L+ voltage for supplying power to the PHY as well as a local controller and additional circuits.

The SN65HVD101 and ’HVD102 are available in the 20-pin RGB package (4 mm × 3,5 mm QFN) for space-constrained applications.

The SN65HVD101 and ‘HVD102 IO-Link PHYs implement the IO-Link interface for industrial point-to-point communication. When the device is connected to an IO-Link master through a 3-wire interface, the master can initiate communication and exchange data with the remote node while the SN65HVD10X acts as a complete physical layer for the communication.

The IO-Link driver output (CQ) can be used in push-pull, high-side, or low-side configurations using the EN and TX input pins. The PHY receiver converts the 24-V IO-Link signal on the CQ pin to standard logic levels on the RX pin. A simple parallel interface is used to receive and transmit data and status information between the PHY and the local controller.

The SN65HVD101 and ’HVD102 implement protection features for overcurrent, overvoltage and overtemperature conditions. The IO-Link driver current limit can be set using an external resistor. If a short-circuit current fault occurs, the driver outputs are internally limited, and the PHY generates an error signal (SC). These devices also implement an overtemperature shutdown feature that protects the device from high-temperature faults.

The SN65HVD102 operates from a single external 3.3-V or 5-V local supply. The SN65HVD101 integrates a linear regulator that generates either 3.3 V or 5 V from the IO-Link L+ voltage for supplying power to the PHY as well as a local controller and additional circuits.

The SN65HVD101 and ’HVD102 are available in the 20-pin RGB package (4 mm × 3,5 mm QFN) for space-constrained applications.
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TIOL111 現行 具整合式突波防護的 IO-Link 裝置收發器 Device offers smaller package, integrated surge protection, and LDO regulator options

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類型 標題 日期
* Data sheet SN65HVD10x IO-Link PHY for Device Nodes datasheet (Rev. D) PDF | HTML 2017年 5月 12日
EVM User's guide SN65HVD101 EVM User's Guide 2013年 1月 3日

設計與開發

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開發板

SN65HVD101EVM — 適用於產品節點 IO-LINK PHY 的 SN65HVD101 和 SN65HVD102 評估模組

The SN65HVD101 and SN65HVD102 IO-LINK PHYs implement the IO-LINK interface for industrial point-to-point communication. When the device is connected to an IO-Link master through a 3-wire interface, the master can initiate communication and exchange data with the remote node while the SN65HVD10X (...)

使用指南: PDF
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模擬型號

SN65HVD101 IBIS Model

SLLM204.ZIP (95 KB) - IBIS Model
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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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模擬工具

TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
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參考設計

TIDA-00188 — IO-Link 感測器發送器參考設計

This reference design offers a rapid prototyping platform for IO-Link sensor transmitter. Due to its modular design, different sections can be easily cut away to allow fast and simple interfacing of any analog or digital sensor.  The design is programmed with a fully validated IO-Link stack (...)
使用指南: PDF
電路圖: PDF
參考設計

TIDA-00457 — 適用於具有類比 4-20mA 輸出的感測器的 IO-Link 轉接器參考設計

TIDA-00457 is an IO-link adapter which evaluates the binary or analog 4-20 mA output signal of sensors in the industrial environment and forwards the results to the PLC via IO-lnk. All this fits in a 6-mm wide PCB compatible with the industry-standard M12 connector.
Design guide: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
VQFN (RGB) 20 Ultra Librarian
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