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LVDS、M-LVDS 和 PECL IC

SN65LVDS047

現行

具有流通針腳的四路 LVDS 驅動器

立即訂購
產品規格表

SN65LVDS047

現行
產品規格表 立即訂購

產品詳細資料

Function Driver Protocols LVDS Number of transmitters 4 Number of receivers 0 Supply voltage (V) 3.3 Signaling rate (Mbps) 400 Input signal CMOS, LVTTL, TTL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Driver Protocols LVDS Number of transmitters 4 Number of receivers 0 Supply voltage (V) 3.3 Signaling rate (Mbps) 400 Input signal CMOS, LVTTL, TTL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 16 59.4 mm² 9.9 x 6 TSSOP (PW) 16 32 mm² 5 x 6.4
  • >400 Mbps (200 MHz) Signaling Rates
  • Flow-Through Pinout Simplifies PCB Layout
  • 300 ps Maximum Differential Skew
  • Propagation Delay Times 1.8 ns (Typical)
  • 3.3 V Power Supply Design
  • ±350 mV Differential Signaling
  • High Impedance on LVDS Outputs on Power Down
  • Conforms to TIA/EIA-644 LVDS Standard
  • Industrial Operating Temperature Range (–40°C to 85°C)
  • Available in SOIC and TSSOP Packages
  • >400 Mbps (200 MHz) Signaling Rates
  • Flow-Through Pinout Simplifies PCB Layout
  • 300 ps Maximum Differential Skew
  • Propagation Delay Times 1.8 ns (Typical)
  • 3.3 V Power Supply Design
  • ±350 mV Differential Signaling
  • High Impedance on LVDS Outputs on Power Down
  • Conforms to TIA/EIA-644 LVDS Standard
  • Industrial Operating Temperature Range (–40°C to 85°C)
  • Available in SOIC and TSSOP Packages

The SN65LVDS047 is a quad differential line driver that implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the four current-mode drivers will deliver a minimum differential output voltage magnitude of 247 mV into a 100- load when enabled.

The intended application of this device and signaling technique is for point-to-point and multi-drop baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.

The SN65LVDS047 is characterized for operation from -40°C to 85°C.

The SN65LVDS047 is a quad differential line driver that implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the four current-mode drivers will deliver a minimum differential output voltage magnitude of 247 mV into a 100- load when enabled.

The intended application of this device and signaling technique is for point-to-point and multi-drop baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.

The SN65LVDS047 is characterized for operation from -40°C to 85°C.
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技術文件

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類型 標題 日期
* Data sheet LVDS Quad Differential Line Driver datasheet (Rev. B) 2003年 12月 1日
Application note Introduction to HVDC Architecture and Solutions for Control and Protection (Rev. B) PDF | HTML 2021年 9月 7日
Application brief LVDS to Improve EMC in Motor Drives 2018年 9月 27日
Application brief How Far, How Fast Can You Operate LVDS Drivers and Receivers? 2018年 8月 3日
Application brief How to Terminate LVDS Connections with DC and AC Coupling 2018年 5月 16日
Technical article Applications of Low Voltage Differential Signaling (LVDS) in Multifunction and Ind PDF | HTML 2017年 8月 24日
Application note An Overview of LVDS Technology 1998年 10月 5日

設計與開發

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模擬型號

SN65LVDS047 IBIS Model D PKG (Rev. A)

SLLC093A.ZIP (7 KB) - IBIS Model
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模擬型號

SN65LVDS047 IBIS Model PW PKG

SLLC212.ZIP (7 KB) - IBIS Model
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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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模擬工具

TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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SOIC (D) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian
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