SN65LVDS047
- >400 Mbps (200 MHz) Signaling Rates
- Flow-Through Pinout Simplifies PCB Layout
- 300 ps Maximum Differential Skew
- Propagation Delay Times 1.8 ns (Typical)
- 3.3 V Power Supply Design
- ±350 mV Differential Signaling
- High Impedance on LVDS Outputs on Power Down
- Conforms to TIA/EIA-644 LVDS Standard
- Industrial Operating Temperature Range (–40°C to 85°C)
- Available in SOIC and TSSOP Packages
The SN65LVDS047 is a quad differential line driver that implements the electrical characteristics
of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage
levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the
switching speeds, and allow operation with a 3.3-V supply rail. Any of the four current-mode
drivers will deliver a minimum differential output voltage magnitude of 247 mV into a 100- load
when enabled.
The intended application of this device and signaling technique is for point-to-point and multi-drop
baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces,
backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation
characteristics of the media, the noise coupling to the environment, and other system characteristics.
The SN65LVDS047 is characterized for operation from -40°C to 85°C.
技術文件
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
SOIC (D) | 16 | Ultra Librarian |
TSSOP (PW) | 16 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。