SN75175

現行

四路差分線路接收器

產品詳細資料

Number of receivers 4 Number of transmitters 0 Duplex Half Supply voltage (nom) (V) 5 Signaling rate (max) (Mbps) 10 IEC 61000-4-2 contact (±V) None Fault protection (V) -10 to 15 Common-mode range (V) -7 to 12 Number of nodes 32 Isolated No Supply current (max) (µA) 70000 Rating Catalog Operating temperature range (°C) 0 to 70
Number of receivers 4 Number of transmitters 0 Duplex Half Supply voltage (nom) (V) 5 Signaling rate (max) (Mbps) 10 IEC 61000-4-2 contact (±V) None Fault protection (V) -10 to 15 Common-mode range (V) -7 to 12 Number of nodes 32 Isolated No Supply current (max) (µA) 70000 Rating Catalog Operating temperature range (°C) 0 to 70
PDIP (N) 16 181.42 mm² 19.3 x 9.4 SOIC (D) 16 59.4 mm² 9.9 x 6 SOP (NS) 16 79.56 mm² 10.2 x 7.8
  • Meet or exceed the requirements of ANSI standard EIA/TIA-422-B, RS-423-B, and RS-485
  • Meet ITU recommendations V.10, V.11, X.26, and X.27
  • Designed for multipoint bus transmission on long bus lines in noisy environments
  • 3-state outputs
  • Common-mode input voltage range: −12 V to 12 V
  • Input sensitivity: ±200 mV
  • Input hysteresis: 50-mV typical
  • High input impedance: 12-kΩ minimum
  • Operate from single 5-V supply
  • Low-power requirements
  • Plug-in replacement for MC3486
  • Meet or exceed the requirements of ANSI standard EIA/TIA-422-B, RS-423-B, and RS-485
  • Meet ITU recommendations V.10, V.11, X.26, and X.27
  • Designed for multipoint bus transmission on long bus lines in noisy environments
  • 3-state outputs
  • Common-mode input voltage range: −12 V to 12 V
  • Input sensitivity: ±200 mV
  • Input hysteresis: 50-mV typical
  • High input impedance: 12-kΩ minimum
  • Operate from single 5-V supply
  • Low-power requirements
  • Plug-in replacement for MC3486

The SN65175 and SN75175 are monolithic quadruple differential line receivers with 3-state outputs. They are designed to meet the requirements of ANSI Standards EIA/TIA-422-B, RS-423-B, and RS-485, and several ITU recommendations. These standards are for balanced multipoint bus transmission at rates up to 10 megabits per second. Each of the two pairs of receivers has a common active-high enable.

The receivers feature high input impedance, input hysteresis for increased noise immunity, and input sensitivity of ±200 mV over a common-mode input voltage range of ±12 V. The SN65175 and SN75175 are designed for optimum performance when used with the SN75172 or SN75174 quadruple differential line drivers.

The SN65175 is characterized for operation from −40°C to 85°C. The SN75175 is characterized for operation from 0°C to 70°C.

The SN65175 and SN75175 are monolithic quadruple differential line receivers with 3-state outputs. They are designed to meet the requirements of ANSI Standards EIA/TIA-422-B, RS-423-B, and RS-485, and several ITU recommendations. These standards are for balanced multipoint bus transmission at rates up to 10 megabits per second. Each of the two pairs of receivers has a common active-high enable.

The receivers feature high input impedance, input hysteresis for increased noise immunity, and input sensitivity of ±200 mV over a common-mode input voltage range of ±12 V. The SN65175 and SN75175 are designed for optimum performance when used with the SN75172 or SN75174 quadruple differential line drivers.

The SN65175 is characterized for operation from −40°C to 85°C. The SN75175 is characterized for operation from 0°C to 70°C.

下載 觀看有字幕稿的影片 影片

您可能會感興趣的類似產品

open-in-new 比較替代產品
引腳對引腳且具備與所比較裝置相同的功能
SN65LBC175A 現行 四路 RS-485 差分線路接收器 Pin-to-pin device offers lower power consumption and higher Data rate

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件,然後再試一次。
檢視所有 1
類型 標題 日期
* Data sheet SNx5175 Quadruple Differential Line Receivers datasheet (Rev. D) PDF | HTML 2023年 10月 16日

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

模擬型號

SN75175 IBIS Model

SCEM495.ZIP (13 KB) - IBIS Model
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
模擬工具

TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
PDIP (N) 16 Ultra Librarian
SOIC (D) 16 Ultra Librarian
SOP (NS) 16 Ultra Librarian

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中持續性的可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

內容係由 TI 和社群貢獻者依「現狀」提供,且不構成 TI 規範。檢視使用條款

若有關於品質、封裝或訂購 TI 產品的問題,請參閱 TI 支援。​​​​​​​​​​​​​​

影片