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LVDS、M-LVDS 和 PECL IC

SN75LVDS9637

現行

高速差分線路接收器

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產品規格表

SN75LVDS9637

現行
產品規格表 立即訂購

產品詳細資料

Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 2 Supply voltage (V) 3.3 Signaling rate (Mbps) 155 Input signal LVDS Output signal LVTTL Rating Catalog Operating temperature range (°C) 0 to 70
Function Receiver Protocols LVDS Number of transmitters 0 Number of receivers 2 Supply voltage (V) 3.3 Signaling rate (Mbps) 155 Input signal LVDS Output signal LVTTL Rating Catalog Operating temperature range (°C) 0 to 70
SOIC (D) 8 29.4 mm² 4.9 x 6
  • Meets or Exceeds the Requirements of ANSI TIA/EIA-644 Standard
  • Operates With a Single 3.3-V Supply
  • Designed for Signaling Rate of up to 155 Mbps
  • Differential Input Thresholds ±100 mV Max
  • Low-Voltage TTL (LVTTL) Logic Output Levels
  • Open-Circuit Fail Safe
  • Characterized For Operation From 0&dg;C to 70°C
  • Meets or Exceeds the Requirements of ANSI TIA/EIA-644 Standard
  • Operates With a Single 3.3-V Supply
  • Designed for Signaling Rate of up to 155 Mbps
  • Differential Input Thresholds ±100 mV Max
  • Low-Voltage TTL (LVTTL) Logic Output Levels
  • Open-Circuit Fail Safe
  • Characterized For Operation From 0&dg;C to 70°C

The SN75LVDS32 and SN75LVDS9637 are differential line receivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the four differential receivers provides a valid logical output state with a ±100 mV allow operation with a differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes.

The intended application of these devices and signaling technique is both point-to-point and multidrop (one driver and multiple receivers) data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The SN75LVDS32 and SN75LVDS9637 are characterized for operation from 0°C to 70°C.

The SN75LVDS32 and SN75LVDS9637 are differential line receivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the four differential receivers provides a valid logical output state with a ±100 mV allow operation with a differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes.

The intended application of these devices and signaling technique is both point-to-point and multidrop (one driver and multiple receivers) data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The SN75LVDS32 and SN75LVDS9637 are characterized for operation from 0°C to 70°C.
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技術文件

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類型 標題 日期
* Data sheet High-Speed Differential Line Receivers datasheet (Rev. B) 2001年 6月 22日
Application brief LVDS to Improve EMC in Motor Drives 2018年 9月 27日
Application brief How Far, How Fast Can You Operate LVDS Drivers and Receivers? 2018年 8月 3日
Application brief How to Terminate LVDS Connections with DC and AC Coupling 2018年 5月 16日
Application note An Overview of LVDS Technology 1998年 10月 5日

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模擬型號

SN65LVDS9637 IBIS Model

SLLC018.ZIP (4 KB) - IBIS Model
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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
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