TFP401A-EP
- Supports Pixel Rates Up to 165 MHz (including 1080p and WUXGA at 60Hz)
- Digital Visual Interface (DVI) Specification Compliant(1)
- True-Color, 24 Bit/Pixel, 16.7M Colors at One or Two Pixels Per Clock
- Laser Trimmed Internal Termination Resistors for Optimum Fixed Impedance Matching
- Skew Tolerant Up to One Pixel Clock Cycle
- 4x Over-Sampling
- Reduced Power Consumption - 1.8 V Core Operation With 3.3 V I/Os and Supplies(2)
- Reduced Ground Bounce Using Time-Staggered Pixel Outputs
- Low Noise and Power Dissipation Using TI PowerPAD Packaging
- Advanced Technology Using TI 0.18-mm EPIC-5 CMOS Process
- TFP401A Incorporates HSYNC Jitter(3)
- SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS
- Controlled Baseline
- One Assembly/Test Site
- One Fabrication Site
- Available in Military (–55°C/125°C) Temperature Range (Custom temperature ranges available)
- Extended Product Life Cycle
- Extended Product-Change Notification
- Product Traceability
(1) The Digital Visual Interface Specification, DVI, is an industry standard developed by the Digital Display Working Group (DDWG) for high-speed digital connection to digital displays. The TFP401A is compliant to the DVI Specification Rev. 1.0.
(2) The TFP401A has an internal voltage regulator that provides the 1.8-V core power supply from the externally supplied 3.3-V supplies.
(3) Immunity The TFP401A incorporates additional circuitry to create a stable HSYNC from DVI transmitters that introduce undesirable jitter on the transmitted HSYNC signal.
PanelBus, PowerPAD, EPIC-5 are trademarks of Texas Instruments.
The Texas Instruments TFP401A is a TI PanelBus™ flat panel display product, part of a comprehensive family of end-to-end DVI 1.0 compliant solutions. Targeted primarily at desktop LCD monitors and digital projectors, the TFP401A finds applications in any design requiring high-speed digital interface. The TFP401A supports display resolutions up to 1080p and WUXGA in 24-bit true color pixel format. The TFP401A offers design flexibility to drive one or two pixels per clock, supports TFT or DSTN panels, and provides an option for time staggered pixel outputs for reduced ground bounce. PowerPAD™ advanced packaging technology results in best of class power dissipation, footprint, and ultra-low ground inductance. The TFP401A combines PanelBus™ circuit innovation with TIs advanced 0.18-mm EPIC-5™ CMOS process technology, along with TI PowerPAD™ package technology to achieve a reliable, low-powered, low-noise, high-speed digital interface solution.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | TI PanelBus Digital Receiver. datasheet (Rev. A) | 2011年 7月 14日 | |
* | Errata | TFP101(A), TFP201(A), TFP401(A) Errata | 2003年 11月 11日 | |
* | Errata | TFP101/A, TFP201/A, TFP401/A, TFP403 Data Sheet Errata | 2003年 6月 27日 | |
* | VID | TFP401A-EP VID V6209627 | 2016年 6月 21日 | |
Application note | How to Bridge HDMI/DVI to LVDS/OLDI (Rev. C) | 2018年 6月 7日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
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封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
HTQFP (PZP) | 100 | Ultra Librarian |
訂購與品質
- RoHS
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