TL16C554A

Name: TL16C554A
Brand: TI
SKU: TL16C554A
Price: 10.197 USD

現行

具有 16 位元組 FIFO 的四路 UART

立即訂購

產品規格表

document-pdfAcrobat Asynchonous Communications Element datasheet (Rev. E) (英文)

TL16C554A

現行

產品規格表

立即訂購

產品詳細資料

Number of channels

4

FIFO (Byte)

16

Rx FIFO trigger levels (#)

4

Programmable FIFO trigger levels

No

CPU interface

X86

Baud rate at Vcc = 3.3 V & with 16x sampling (max) (Mbps)

1

Baud rate at Vcc = 5 V & with 16x sampling (max) (Mbps)

1

Operating voltage (V)

3.3, 5

Auto RTS/CTS

Yes

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Number of channels

4

FIFO (Byte)

16

Rx FIFO trigger levels (#)

4

Programmable FIFO trigger levels

No

CPU interface

X86

Baud rate at Vcc = 3.3 V & with 16x sampling (max) (Mbps)

1

Baud rate at Vcc = 5 V & with 16x sampling (max) (Mbps)

1

Operating voltage (V)

3.3, 5

Auto RTS/CTS

Yes

Rating

Catalog

Operating temperature range (°C)

-40 to 85

LQFP (PM)

64

144 mm² 12 x 12

LQFP (PN)

80

196 mm² 14 x 14

PLCC (FN)

68

632.5225 mm² 25.15 x 25.15

Integrated Asynchronous-Communications Element
Consists of Four Improved TL16C550C ACEs Plus Steering Logic
In FIFO Mode, Each ACE Transmitter and Receiver Is Buffered
With 16-Byte FIFO to Reduce the Number of Interrupts to CPU
In TL16C450 Mode, Hold and Shift Registers Eliminate Need for Precise
Synchronization Between the CPU and Serial Data
Up to 16-MHz Clock Rate for up to 1-Mbaud Operation with V_CC = 3.3 V and 5 V
Programmable Baud-Rate Generators Which Allow Division of Any Input Reference Clock
by 1 to (2¹⁶ – 1) and Generate an Internal 16 × Clock
Adds or Deletes Standard Asynchronous Communication Bits (Start, Stop, and
Parity) to or From the Serial-Data Stream
Independently Controlled Transmit, Receive, Line Status, and Data Set Interrupts
5-V and 3.3-V Operation
Fully Programmable Serial Interface Characteristics:
- 5-, 6-, 7-, or 8-Bit Characters
- Even-, Odd-, or No-Parity Bit
- 1-, 1 1/2-, or 2-Stop Bit Generation
- Baud Generation (DC to 1-Mbit Per Second)
False Start Bit Detection
Complete Status Reporting Capabilities
Line Break Generation and Detection
Internal Diagnostic Capabilities:
- Loopback Controls for Communications Link Fault Isolation
- Break, Parity, Overrun, Framing Error Simulation
Fully Prioritized Interrupt System Controls
Modem Control Functions (CTS, RTS, DSR, DTR, RI, and DCD)
3-State Outputs Provide TTL Drive Capabilities for Bidirectional Data Bus
and Control Bus
Programmable Auto-RTS and Auto-CTS
CTS Controls Transmitter in Auto-CTS Mode,
RCV FIFO Contents and Threshold Control RTS in Auto-RTS Mode,

Integrated Asynchronous-Communications Element
Consists of Four Improved TL16C550C ACEs Plus Steering Logic
In FIFO Mode, Each ACE Transmitter and Receiver Is Buffered
With 16-Byte FIFO to Reduce the Number of Interrupts to CPU
In TL16C450 Mode, Hold and Shift Registers Eliminate Need for Precise
Synchronization Between the CPU and Serial Data
Up to 16-MHz Clock Rate for up to 1-Mbaud Operation with V_CC = 3.3 V and 5 V
Programmable Baud-Rate Generators Which Allow Division of Any Input Reference Clock
by 1 to (2¹⁶ – 1) and Generate an Internal 16 × Clock
Adds or Deletes Standard Asynchronous Communication Bits (Start, Stop, and
Parity) to or From the Serial-Data Stream
Independently Controlled Transmit, Receive, Line Status, and Data Set Interrupts
5-V and 3.3-V Operation
Fully Programmable Serial Interface Characteristics:
- 5-, 6-, 7-, or 8-Bit Characters
- Even-, Odd-, or No-Parity Bit
- 1-, 1 1/2-, or 2-Stop Bit Generation
- Baud Generation (DC to 1-Mbit Per Second)
False Start Bit Detection
Complete Status Reporting Capabilities
Line Break Generation and Detection
Internal Diagnostic Capabilities:
- Loopback Controls for Communications Link Fault Isolation
- Break, Parity, Overrun, Framing Error Simulation
Fully Prioritized Interrupt System Controls
Modem Control Functions (CTS, RTS, DSR, DTR, RI, and DCD)
3-State Outputs Provide TTL Drive Capabilities for Bidirectional Data Bus
and Control Bus
Programmable Auto-RTS and Auto-CTS
CTS Controls Transmitter in Auto-CTS Mode,
RCV FIFO Contents and Threshold Control RTS in Auto-RTS Mode,

The TL16C554A is an enhanced quadruple version of the TL16C550C asynchronous-communications element (ACE). Each channel performs serial-to-parallel conversion on data characters received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The complete status of each channel of the quadruple ACE can be read by the CPU at any time during operation. The information obtained includes the type and condition of the operation performed and any error conditions encountered.

The TL16C554A quadruple ACE can be placed in an alternate FIFO mode, which activates the internal FIFOs to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in both receive and transmit modes. In the FIFO mode of operation, there is a selectable autoflow control feature that can significantly reduce software overhead and increase system efficiency by automatically controlling serial-data flow using RTS output and CTS input signals. All logic is on the chip to minimize system overhead and maximize system efficiency. Two terminal functions allow signaling of direct-memory access (DMA) transfers. Each ACE includes a programmable baud-rate generator that can divide the timing reference clock input by a divisor between 1 and 2¹⁶ – 1.

The TL16C554A is available in a 68-pin plastic-leaded chip-carrier (PLCC) FN package, 64-pin plastic quad flatpack (PQFP) PM package and in an 80-pin (TQFP) PN package.

The TL16C554A is an enhanced quadruple version of the TL16C550C asynchronous-communications element (ACE). Each channel performs serial-to-parallel conversion on data characters received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The complete status of each channel of the quadruple ACE can be read by the CPU at any time during operation. The information obtained includes the type and condition of the operation performed and any error conditions encountered.

The TL16C554A quadruple ACE can be placed in an alternate FIFO mode, which activates the internal FIFOs to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in both receive and transmit modes. In the FIFO mode of operation, there is a selectable autoflow control feature that can significantly reduce software overhead and increase system efficiency by automatically controlling serial-data flow using RTS output and CTS input signals. All logic is on the chip to minimize system overhead and maximize system efficiency. Two terminal functions allow signaling of direct-memory access (DMA) transfers. Each ACE includes a programmable baud-rate generator that can divide the timing reference clock input by a divisor between 1 and 2¹⁶ – 1.

The TL16C554A is available in a 68-pin plastic-leaded chip-carrier (PLCC) FN package, 64-pin plastic quad flatpack (PQFP) PM package and in an 80-pin (TQFP) PN package.

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