TLIN1028S-Q1
- AEC-Q100 (Grade 1) : Qualified for automotive applications
- Local interconnect network (LIN) physical layer specification ISO/DIS 17987–4 compliant and conforms to SAE J2602 recommended practice for LIN (See SLLA495)
- Functional Safety-Capable
- Supports 12-V applications
- Wide operating ranges
- ±58 V LIN bus fault protection
- LDO output supporting 3.3 V or 5 V
- Sleep mode: Ultra-low current consumption allows wake-up event from:
- LIN bus or local wake through EN pin
- Power-up and down glitch-free operation
- Protection features:
- ESD protection, VSUP under-voltage protection
- TXD dominant time out (DTO) protection, Thermal shutdown
- Unpowered node or ground disconnection fail-safe at system level
- VCC sources up to 70 mA
- Available in SOIC (8) package
The TLIN1028S-Q1 is a local interconnect network (LIN) physical layer transceiver, compliant to LIN 2.2A ISO/DIS 17987–4 standards, with an integrated low dropout (LDO) voltage regulator.
LIN is a single-wire bidirectional bus typically used for low speed in-vehicle networks using data rates up to 20 kbps. The LIN receiver supports data rates up to 100 kbps for end-of-line programming. The TLIN1028S-Q1 converts the LIN protocol data stream on the TXD input into a LIN bus signal. The receiver converts the data stream to logic-level signals that are sent to the microprocessor through the open-drain RXD pin. The TLIN1028S-Q1 reduces system complexity by providing a 3.3 V or 5 V rail with up to 70 mA of current to power microprocessors, sensors or other devices. The TLIN1028S-Q1 has an optimized current-limited wave-shaping driver which reduces electromagnetic emissions (EME).
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | TLIN1028S-Q1 Automotive 70-mA System Basis Chip (SBC) datasheet (Rev. B) | PDF | HTML | 2022年 5月 31日 |
* | Errata | TLIN1028S-Q1 Duty Cycle Over VSUP | 2020年 5月 22日 | |
User guide | TLIN1028x EVM User's Guide (Rev. A) | PDF | HTML | 2022年 2月 11日 | |
Functional safety information | TLIN1028xS-Q1 Functional Safety FIT Rate, Failure Mode Distribution and Pin FMA (Rev. A) | PDF | HTML | 2020年 10月 13日 |
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
TLIN1028EVM — 具有整合式 LDO 和 MCU 重設的 TLIN1028 LIN 系統基礎晶片評估模組
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
SOIC (D) | 8 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。