TPS3813K33-EP
- Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
- Extended Temperature Performance of -55°C to 125°C
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product-Change Notification
- Qualification Pedigree(1)
- Window-Watchdog With Programmable Delay and Window Ratio
- 6-Pin SOT-23 Package
- Supply Current of 9 µA (Typ)
- Power On Reset Generator With a Fixed Delay Time of 25 ms
- Precision Supply Voltage Monitor 2.5 V, 3 V, 3.3 V, 5 V
- Open-Drain Reset Output
- APPLICATIONS
- Applications Using DSPs, Microcontrollers, or Microprocessors
- Safety Critical Systems
- Automotive Systems
- Healing Systems
(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
The TPS3813 family of supervisory circuits provides circuit initialization and timing supervision, primarily for DSPs and processor-based systems.
During power on, RESET is asserted when supply voltage (VDD) becomes higher than 1.1 V. Thereafter, the supervisory circuit monitors VDD and keeps RESET active as long as VDD remains below the threshold voltage (VIT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, td = 25 ms typical, starts after VDD has risen above the threshold voltage (VIT). When the supply voltage drops below the threshold voltage (VIT), the output becomes active (low) again. No external components are required. All the devices of this family have a fixed-sense threshold voltage (VIT) set by an internal voltage divider.
For safety critical applications the TPS3813 family incorporates a so-called window-watchdog with programmable delay and window ratio. The upper limit of the watchdog time-out can be set by either connecting WDT to GND, VDD, or using an external capacitor. The lower limit and thus the window ratio is set by connecting WDR to GND or VDD. The supervised processor now needs to trigger the TPS3813 within this window not to assert a RESET.
The product spectrum is designed for supply voltages of 2.5 V, 3 V, 3.3 V, and 5 V. The circuits are available in a 6-pin SOT-23 package.
The TPS3813 devices are characterized for operation over a temperature range of -55°C to 125°C.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | TPS3813J25-EP, TPS3813L30-EP, TPS3813K33-EP, TPS3813I50-EP datasheet (Rev. A) | 2006年 5月 24日 | |
* | Radiation & reliability report | TPS3813K33MDBVREP Reliability Report | 2016年 10月 5日 | |
* | VID | TPS3813K33-EP VID V6206627 | 2016年 6月 21日 | |
E-book | Voltage Supervisor and Reset ICs: Tips, Tricks and Basics | 2019年 6月 28日 | ||
Application note | All Window Watchdog Supervisors | 2009年 9月 9日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
SOT-23 (DBV) | 6 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點