TPS40042
- 3.0-V to 5.5-V Input
- External Reference required: 0.5 V to 1.5 V
- Output Voltage from REFIN to 90% of VIN
- High-Side Drive for N-Channel FET
- Supports Pre-Biased Outputs
- Adaptive Anti-Cross Conduction Gate Drive
- Fixed switching frequency (600 kHz) Voltage Mode Control
- Three Selectable Short Circuit Protection Levels
- Hiccup Restart from Faults
- Active Low Enable
- Thermal Shutdown Protection at 145°C
- 10-Pin, 3-mm x 3-mm SON (DRC)
- APPLICATIONS
- DDR Memory
- Point of Load
- Telecommunications
- DC to DC Modules
Predictive Gate Drive Is a trademark of Texas Instruments.
The TPS40042 DC/DC controller is designed to operate with an input source between a 3.0 V and 5.5 V. To reduce the number of external components, a number of operating parameters are fixed internally. The operating frequency for example, is internally set at 600 kHz.
One of three short circuit threshold levels may be selected by the addition of an external resistor from the COMP pin to circuit ground (no resistor is the default setting). During power on, and before the internal soft start commands the output voltage to rise, the TPS40042 enters a calibration cycle, measures the current out of the COMP pin, and selects an internal SCP threshold voltage. At the end of the 1.5-ms calibration time, the output voltage is allowed to enter soft-start. During operation, the selected SCP threshold voltage is compared to the upper MOSFET’s voltage drop during its ON time to determine whether there is an overload condition. If the voltage across the MOSFET exceeds the threshold voltage, the TPS40042 counts seven continuous pulses before shutting completely OFF for seven soft start charge/discharge cycles, after which, the TPS40042 attempts to restart the output.
During startup, both the high-side MOSFET switch and the synchronous rectifier are held in the OFF state until the internal soft start commands an output voltage higher than the voltage currently at the output. This may happen when the output is pre-biased at some voltage greater than zero and less than the desired regulation voltage. When the internal soft start first commands the output to rise, the pulse width of the synchronous rectifier is slowly increased from zero to the full 1-D conduction time by a number of discrete steps. In this way, inductor current is not allowed to reverse quickly, and ensures a monotonic startup of the output whether the output starts from zero or from a pre-bias level. If power is applied to the device while the EN (enable low) pin is allowed to float high, the TPS40042 remains OFF. Only when the EN pin is pulled down towards ground is the controller allowed to start.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | Low Pin Count, Low VIN [3.0V to 5.5V] Synchronous Buck DC-to-DC Controller datasheet | 2007年 6月 22日 | |
| Selection guide | Power Management Guide 2018 (Rev. R) | 2018年 6月 25日 |
設計與開發
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TPS40042 Unencrypted PSpice Transient Model Package (Rev. A)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VSON (DRC) | 10 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點